Datasheet

Automotive Power-Management IC with
Three Step-Down Converters and Linear Regulator
MAX16920
14
Undervoltage Output (UVO)
The MAX16920 features an active-low undervoltage
output (UVO) to monitor the input voltage. UVO is pulled
low when the voltage at UVI falls below 1.205V. To
monitor battery voltage, connect a resistive divider
between the battery, UVI, and UVS. An undervoltage
condition asserts the UVO flag only and does not effect
the regulator outputs.
In case only DC-DC1 is running, UVO is high impedance.
For more details, see the Setting the Undervoltage
Output (UVO) Level section.
Overvoltage Output (ODRV)
The MAX16920 features an overvoltage output (ODRV)
that can be used to create an overvoltage-protected
battery output with the addition of an external pMOS
transistor. If V
INA
exceeds 19.2V (typ), the ODRV out-
put is driven high, which turns off the external pMOS.
An overvoltage condition does not affect any of the
other MAX16920 converters.
Choose an external pMOS transistor with a low-enough
R
DSON
so that voltage loss and power dissipation at
the nominal output current are acceptable. Very low
R
DSON
pMOS transistors have larger effective input
capacitance and thus are switched more slowly by the
ODRV output. When only DC-DC1 is running, ODRV is
high and the external pMOS is off.
Overtemperature Protection (OT)
The MAX16920 features an active-low overtemperature
output (OT). The MAX16920 pulls the OT output low and
disables all the regulators except DC-DC1, if the die
temperature exceeds the thermal shutdown temperature
(T
S
).
Applications Information
Inductor Selection
Three key inductor parameters must be specified for
operation with the MAX16920: inductance value (L),
peak inductor current (I
PEAK
), and inductor satura-
tion current (I
SAT
). The minimum required inductance
is a function of operating frequency, input-to-output
voltage differential, and the peak-to-peak inductor current
(ΔI
P-P
). Higher ΔI
P-P
allows for a lower inductor value,
while a lower ΔI
P-P
requires a higher inductor value. A
lower inductor value minimizes size and cost, improves
large-signal and transient response, but reduces
efficiency due to higher peak currents and higher
peak-to-peak output-voltage ripple for the same output
capacitor. On the other hand, higher inductance
increases efficiency by reducing the ripple current.
Resistive losses due to extra wire turns can exceed the
benefit gained from lower ripple current levels, especial-
ly when the inductance is increased without also allow-
ing for larger inductor dimensions. A good compromise
is to choose ΔI
P-P
equal to 30% of the full load current.
Use the following equation to calculate the inductance:
L = V
OUT
(V
IN
– V
OUT
)/(V
IN
x f
SW
x ΔI
P-P
)
V
IN
and V
OUT
are typical values so that efficiency is optimum
for typical conditions. The peak-to-peak inductor current,
which reflects the peak-to-peak output ripple, is larger at the
maximum input voltage. See the Output Capacitor Selection
section to verify that the worst-case output ripple is
acceptable. The inductor saturation current is also impor-
tant to avoid runaway current during continuous output
short circuit. Choose an inductor with a saturation cur-
rent of greater than the maximum current limit
to ensure
proper operation and avoid runaway.
Input Capacitor Selection
The discontinuous input current of the buck converter
causes large input ripple current. The switching fre-
quency, peak inductor current, and the allowable peak-
to-peak input-voltage ripple dictate the input capaci-
tance requirement. Increasing the switching frequency
or the inductor value lowers the peak-to-average current
ratio, yielding a lower input capacitance requirement.
The input ripple consists mainly of ΔV
Q
(caused by the
capacitor discharge) and ΔV
ESR
(caused by the ESR of
the input capacitor). The total voltage ripple is the sum
of ΔV
Q
and ΔV
ESR
. Assume the input voltage ripple from
the ESR and the capacitor discharge is equal to 50%
each. The following equations show the ESR and capaci-
tor requirement for a target voltage ripple at the input:
ESR
P–P
OUT
OUT
IN
Q SW
V
ESR
I
I
2
I x D(1– D)
C
V x f
∆
=
∆
 
+
 
 
=
∆
where:
( )
( )
IN OUT OUT
P–P
IN SW
V – V x V
I
V x f x L
∆ =