Datasheet

Detailed Description
The Typical Operating Circuit shows a typical connec-
tion for the MAX16033–MAX16040. OUT powers the
static random-access memory (SRAM). If V
CC
is greater
than the reset threshold (V
TH
), or if V
CC
is lower than
V
TH
but higher than V
BATT
, V
CC
is connected to OUT.
If V
CC
is lower than V
TH
and V
CC
is less than V
BATT
,
BATT is connected to OUT. OUT supplies up to 200mA
from V
CC
. In battery-backup mode, an internal MOSFET
connects the backup battery to OUT. The on-resistance
of the MOSFET is a function of the backup-battery volt-
age and temperature and is shown in the BATT-to-OUT
On-Resistance vs. Temperature graph in the Typical
Operating Characteristics.
Chip-Enable Signal Gating
(MAX16033–MAX16036 Only)
The MAX16033–MAX16036 provide internal gating of
chip-enable (CE) signals to prevent erroneous data from
being written to CMOS RAM in the event of a power fail-
ure or brownout condition. During normal operation, the
CE gate is enabled and passes all CE transitions. When
reset asserts, this path becomes disabled, preventing
erroneous data from corrupting the CMOS RAM. The
MAX16033–MAX16036 provide a series transmission
gate from CEIN to CEOUT. A 2ns (typ) propagation delay
from CEIN to CEOUT allows these devices to be used
with most μPs and high-speed DSPs.
When RESET is deasserted, CEIN is connected to
CEOUT through a low on-resistance transmission gate. If
CEIN is high when RESET is asserted, CEOUT remains
high regardless of any subsequent transitions on CEIN
during the reset event.
If CEIN is low when RESET is asserted, CEOUT is held
low for 1μs to allow completion of the read/write operation
(Figure 1). After the 1μs delay expires, CEOUT goes high
and stays high regardless of any subsequent transitions
on CEIN during the reset event. When CEOUT is discon-
nected from CEIN, CEOUT is actively pulled up to OUT.
The propagation delay through the chip-enable circuitry
depends on both the source impedance of the drive to
CEIN and the capacitive loading at CEOUT. The chip-
enable propagation delay is specified from the 50% point
of CEIN to the 50% point of CEOUT, using a 50Ω driver
and 50pF load capacitance. Minimize the capacitive load
at CEOUT and use a low output-impedance driver to
minimize propagation delay.
In high-impedance mode, the leakage current at CEIN is
±1μA (max) over temperature. In low-impedance mode,
the impedance of CEIN appears as a 75Ω resistor in
series with the load at CEOUT.
Figure 1. RESET and Chip-Enable Timing
V
CC
V
TH
t
RD
t
RD
t
RP
t
RP
CEIN
CEOUT
RESET
PFO
PFI > V
PFI
RESET-TO-CEOUT DELAY
*
* IF CEIN GOES HIGH BEFORE RESET ASSERTS,
CEOUT GOES HIGH WITHOUT DELAY AS CEIN GOES HIGH.
MAX16033–MAX16040 Low-Power Battery-Backup
Circuits in Small μDFN Packages
www.maximintegrated.com
Maxim Integrated │ 9