Datasheet

MAX16000–MAX16007
Low-Voltage, Quad-/Hex-/Octal-Voltage
µP Supervisors
10
Maxim Integrated
Pin Description (MAX16006/MAX16007)
PIN
MAX16006 MAX16007
NAME FUNCTION
1 1 IN5 Monitored Input Voltage 5. See Table 1 for the input voltage threshold.
2 2 IN6 Monitored Input Voltage 6. See Table 1 for the input voltage threshold.
3 3 IN7 Monitored Input Voltage 7. See Table 1 for the input voltage threshold.
4 4 IN8 Monitored Input Voltage 8. See Table 1 for the input voltage threshold.
5 5 WDI
Watchdog Timer Input. If WDI remains low or high for longer than the watchdog timeout period,
RESET is asserted and the timer is cleared. The timer also clears whenever a reset is asserted or a
rising or falling edge on WDI is detected. The watchdog timer enters a startup period that allows 54s
for the first transition to occur before a reset. Leave WDI unconnected to disable the watchdog timer.
The WDI open-state detector uses a small 400nA current. Therefore, do not connect WDI to anything
that will source or sink more than 200nA. Note that the leakage current specification for most three-
state drivers exceeds 200nA.
6 6 GND Ground
77 V
CC
Unmonitored Power-Supply Input
8 — OUT5
Output 5. When the voltage at IN5 falls below its threshold, OUT5 goes low and stays low until the
voltage at IN5 exceeds its threshold. The open-drain output has a 30µA internal pullup to V
CC
.
9 — OUT6
Output 6. When the voltage at IN6 falls below its threshold, OUT6 goes low and stays low until the
voltage at IN6 exceeds its threshold. The open-drain output has a 30µA internal pullup to V
CC
.
10 — OUT7
Output 7. When the voltage at IN7 falls below its threshold, OUT7 goes low and stays low until the
voltage at IN7 exceeds its threshold. The open-drain output has a 30µA internal pullup to V
CC
.
11 — OUT8
Output 8. When the voltage at IN8 falls below its threshold, OUT8 goes low and stays low until the
voltage at IN8 exceeds its threshold. The open-drain output has a 30µA internal pullup to V
CC
.
12 10 MR
Active-Low Manual Reset Input. Pull MR low to assert RESET low. RESET remains low for the reset
timeout period after MR is deasserted. MR is pulled up to V
CC
through a 20kΩ resistor.
13 11 SRT
Set Reset Timeout Input. Connect a capacitor from SRT to GND to set the reset timeout period. The
reset timeout period can be calculated as follows:
Reset Timeout (s) = 2.06 x 10
6
(Ω) x C
SRT
(F). For the internal timeout period of 140ms (min), connect
SRT to V
CC
.