Datasheet

Figure 3. Write and Read Timing
t
CWS
t
WR
t
WBD
t
CONV
t
BRD
t
BWD
t
ACQ
t
RDL
t
RDH
t
RDL
t
WRD
t
CWH
t
CRS
t
CRH
t
CRS
t
CRH
t
CRS
DATA IN DATA OUT DATA OUT
t
AH
t
AS
t
DV
t
DV
t
tR
t
tR
CS
WR
RD
BUSY
D0–D7
MODE
V
SS
AGND
1
2
24
23
AIN1
AIN0 AIN3
V
DD
AIN2
PDIP
TOP VIEW
3
4
22
21
WR
BUSY D1/A1
5
6
20
19
CS
RD REFOUT
D0/A0
REFIN
7
8
18
17
CLK D2
9 16
D7/ALL D3/PD
10 15
D6/DIFF D4/INH
11 14
DGND D5/BIP
12 13
MAX156
+
AIN3
N.C.AIN0
1
2
28
27
AIN2
N.C.AIN1
N.C.
N.C
WIDE SO
3
4
26
25
AGND
REFIN
CS
5 24 V
DD
MODE
V
SS
6
7
23
22
REFOUTRD
8 21
D0/A0WR
9 20
D1/A1BUSY
10 19
D2CLK
11 18
D3/PDD7/ALL
12 17
D4/INHD6/DIFF
13 16
D5/BIPDGND
14 15
+
MAX156
AIN1
AIN0 AIN7
1
2
28
27
AIN3
AIN2 AIN5
AIN6
AIN4
PDIP/SO
3
4
26
25
CS
RD REFOUT
5
6
24
23
MODE
V
SS
AGND
REFIN
V
DD
7
8
22
21
WR D0/A0
9 20
BUSY D1/A1
10 19
CLK D2/A2
11 18
D7/ALL
D6/DIFF
DGND
D3/PD
D4/INH
D5/BIP
12 17
13 16
14 15
+
MAX155
MAX155/MAX156 8-/4-Channel ADCs with Simultaneous
T/Hs and Reference
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Pin Conguration