Datasheet

Figure 7a. Hard-Wired Mode Timing—Eight Single-Ended Conversions
Figure 7b. Hard-Wired Mode Timing—Eight Single-Ended Conversions
CH0 CH1 CH6 CH7
t
CONV
END OF CONVERSION
OF 8 CHANNELS
THE FIRST RAM
LOCATION
READ IS CH 0
CONSECUTIVE RAM LOCATIONS ARE
ACCESSED BY CONSECUTIVE RD PULSES
MODE = 0
ALL 8 CHANNELS ARE
SAMPLED HERE
CS
WR
RD
BUSY
D0-D7
0, 1 2, 3 4, 5 6, 7
t
CONV
END OF CONVERSION
OF 4 DIFFERENTIAL
CHANNELS
THE FIRST RAM
LOCATION
READ IS CH 0, 1
CONSECUTIVE RAM LOCATIONS ARE
ACCESSED BY CONSECUTIVE RD PULSES
MODE = 1
ALL 4 DIFFERENTIAL CHANNELS
SAMPLED HERE
CS
WR
RD
BUSY
D0–D7
MAX155/MAX156 8-/4-Channel ADCs with Simultaneous
T/Hs and Reference
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