Datasheet

Figure 4a. Input/Output Mode Timing–Eight Single-Ended Conversions
t
CONV
CS
WR
RD
BUSY
D0-D7
DATA IN
CONVERSION END
OF ALL 8 CHANNELS
ACCESSED BY CONSECUTIVE RD PULSES
CONSECUTIVE RAM LOCATIONS ARE
UPDATE CONFIGURATION
REGISTER AND BEGIN NEW
CONVERSION
ALL 8 CHANNELS ARE SAMPLED HERE
NOTE: After power-up, and prior to the above
timing sequence, all single-ended channels must
be set up by writing the following data into the
configuration register. 8 WRs (see Figure 3) are
needed for 8 channels:
A0 A1 A2 PD INH BIP DIFF ALL
0 0 0 0 1 S 0 0
1 0 0 0 1 S 0 0
0 1 0 0 1 S 0 0
1 1 0 0 1 S 0 0
0 0 1 0 1 S 0 0
1 0 1 0 1 S 0 0
0 1 1 0 1 S 0 0
1 1 1 0 1 S 0 0
CH0 CH1 CH2 CH3
Once the above data is loaded, all channels are
converted with a single WR to any address
(this is where the above timing diagram begins).
With INH = 0, and ALL = 0:
THE FIRST RAM
LOCATION READ
IS CH 0
S = May be selected
A0 A1 A2 PD INH BIP DIFF ALL
0 0 0 0 0 S 0 0
MAX155/MAX156 8-/4-Channel ADCs with Simultaneous
T/Hs and Reference
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