Datasheet

MAX153 1Msps, µP-Compatible,
8-Bit ADC with 1µA Power-Down
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Detailed Description
Converter Operation
The MAX153 uses a half-flash conversion technique (see
the Functional Diagram) in which two 4-bit flash ADC
sectionsachieve an 8-bit result. Using 15 comparators,
theflashADCcomparestheunknowninputvoltagetothe
reference ladder and provides the upper 4 data bits.
An internal digital-to-analog converter (DAC) uses the 4
mostsignificantbits(MSBs)togeneratetheanalogresult
from the first flash conversion and a residue voltage that
isthedifferencebetweentheunknowninputandtheDAC
voltage. The residue is then compared again with the
flashcomparatorstoobtainthelower4databits(LSBs).
Power-Down Mode
In burst-mode or low sample-rate applications, the
MAX153 can be shut down between conversions, reduc-
ingsupplycurrenttomicroamplevels.ATTL/CMOSlog-
ic-low on the PWRDN pin shuts the device down, reduc-
ing supply current to typically 1µA when powered from a
single 5V supply. CS must be high when power- down is
used. A logic-high on PWRDNwakesuptheMAX153.A
new conversion can be started (WR asserted low) within
360ns of the PWRDN pin being driven high 200ns to
powerupplus160nsfortrack/holdacquisition).Ifpower-
down mode is not required, connect PWRDN to V
DD
.
Once the MAX153 is in power-down mode, lowest sup-
plycurrentis drawn withMODE low (RDmode)due to
an internal 50µA pulldown resistor at this pin. CS must
remain high during shutdown because the MAX153 may
attempt to start a conversion that it cannot complete. In
addition, for minimum current consumption, other digital
inputs should remain stable in power-down. RDY, an
open-drainoutput(inRDmode),willthenfallandremain
low throughout. Power-down, sinking additional supply
current unless CSremainshigh.SeetheReference sec-
tion for information on reducing reference current during
power-down.
Digital Interface
The MAX153 has two basic interface modes set by the
statusof the MODE input pin. When MODE is low, the
converter is in the RD mode; when MODE is high, the
converterissetupfortheWR-RDmode.
Read Mode (MODE = 0)
InRDmode,conversioncontrolanddataaccessarecon-
trolled by the RDinput(Figure3).Thecomparatorinputs
track the analog input voltage for the duration of t
P
. A
minimum of 160ns is required for the input to be acquired.
A conversion is initiated by driving RD low. With µPs that
can be forced into a wait state, hold RD low until output
data appears. The µP starts the conversion, waits, and
then reads data with a single read instruction.
WR/RDY is configured as a status output (RDY) in RD
mode, where it can drive the ready or wait input of a µP.
RDYisanopen-collectoroutput(withnointernalpullup)
that goes low after the falling edge of CS and goes high
at the end of the conversion. If not used, the WR/RDYpin
can be left unconnected. The INT output goes low at the
end of the conversion and returns high on the rising edge
of CS or RD.
Write-Read Mode (MODE = 1)
Figures 4 and 5 show the operating sequence for the
write-read(WR-RD)mode.Thecomparatorinputs track
the analog input voltage for the duration of t
P
. A minimum
of 160ns is required for the input voltage to be acquired.
The conversion is initiated by a falling edge of WR. When
WRreturnshigh,the4MSBsflashresultislatchedinto
theoutputbuffersandthe4LSBsconversionbegins.INT
goes low about 380ns later, indicating conversion end,
and the lower 4 data bits are latched into the output buf-
fers.Thedataisthenaccessible65nsto130nsafterRD
goes low (see the Timing Characteristics).
If an externally controlled conversion time is required,
drive RD low 250ns after WR goes high. This latches
the lower 4 data bits and outputs the conversion result
on D0–07. A minimum 160ns delay is required from INT
going low to the start of another conversion (WR going
low).
Options for reading data from the converter include the
following:
Using Internal Delay
The µP waits for the INT output to go low before reading
thedata(Figure4).INT typically goes low 380ns after the
rising edge of WR, indicating the conversion is complete,
and the result is available in the output latch. With CS low,
data outputs D0–D7 can be accessed by pulling RD low.
INT is then reset by the rising edge of CS or RD.