Datasheet

MAX1533A/MAX1537A
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
20 ______________________________________________________________________________________
SMPS Enable Controls (ON3, ON5)
ON3 and ON5 control SMPS power-up sequencing.
ON3 or ON5 rising above 2.4V enables the respective
outputs. ON3 or ON5 falling below 1.6V disables the
respective outputs. Driving ON_ below 0.8V clears the
overvoltage, undervoltage, and thermal fault latches.
SMPS Power-Up Sequencing
Connecting ON3 or ON5 to REF forces the respective
outputs off while the other output is below regulation
and starts after that output regulates. The second SMPS
remains on until the first SMPS turns off, the device
shuts down, a fault occurs, or LDO5 goes into undervolt-
age lockout. Both supplies begin their power-down
sequence immediately when the first supply turns off.
Output Discharge (Soft-Shutdown)
When output discharge is enabled (OVP pulled low)
and the switching regulators are disabled—by transi-
tions into standby or shutdown mode, or when an
output undervoltage fault occurs—the controller dis-
charges both outputs through internal 12Ω switches,
until the output voltages decrease to 0.3V. This slowly
discharges the output capacitance, providing a soft-
damped shutdown response. This eliminates the slight-
ly negative output voltages caused by quickly
discharging the output through the inductor and low-
side MOSFET. When an SMPS output discharges to
0.3V, its low-side driver (DL_) is forced high, clamping
the respective SMPS output to GND. The reference
remains active to provide an accurate threshold and to
provide overvoltage protection. Both SMPS controllers
contain separate soft-shutdown circuits.
When output discharge is disabled (OVP = V
CC
), the low-
side drivers (DL_) and high-side drivers (DH_) are both
pulled low, forcing LX into a high-impedance state. Since
the outputs are not actively discharged by the SMPS con-
trollers, the output-voltage discharge rate is determined
only by the output capacitance and load current.
Fixed-Frequency, Current-Mode
PWM Controller
The heart of each current-mode PWM controller is a multi-
input, open-loop comparator that sums two signals: the
output-voltage error signal with respect to the reference
voltage and the slope-compensation ramp (Figure 3).
The MAX1533A/MAX1537A use a direct-summing con-
figuration, approaching ideal cycle-to-cycle control over
the output voltage without a traditional error amplifier and
the phase shift associated with it. The MAX1533A/
MAX1537A use a relatively low loop gain, allowing the
use of low-cost output capacitors. The low loop gain
results in the -0.1% typical load-regulation error and
helps reduce the output capacitor size and cost by
shifting the unity-gain crossover frequency to a lower
level.
Table 3. Operating Modes
INPUTS* OUTPUTS
MODE
SHDN ON5 ON3 LDO5 LDO3 5V SMPS 3V SMPS
Shutdown Mode LOW X X OFF OFF OFF OFF
Standby Mode HIGH LOW LOW ON ON OFF OFF
Normal Operation HIGH HIGH HIGH ON ON ON ON
3.3V SMPS Active HIGH LOW HIGH ON ON OFF ON
5V SMPS Active HIGH HIGH LOW ON ON ON OFF
Normal Operation
(Delayed 5V SMPS
Startup)
HIGH REF HIGH ON ON
ON
Power-up after
3.3V SMPS is in
regulation
ON
Normal Operation
(Delayed 3.3V
SMPS Startup)
HIGH HIGH REF ON ON ON
ON
Power-up after
5V SMPS is in
regulation
* SHDN is an accurate, low-voltage logic input with 1V falling-edge threshold voltage and 1.6V rising-edge threshold voltage. ON3
and ON5 are 3-level CMOS logic inputs, a logic-low voltage is less than 0.8V, a logic-high voltage is greater than 2.4V, and the mid-
dle logic level is between 1.9V and 2.1V (see the
Electrical Characteristics table).