Datasheet

the desired delay for the controller that starts last (ONLd).
Using 0.1μF for C1 provides about 16ms total delay.
Because of the 6μA current flowing through R1 (51kΩ),
the voltage on ONLc is 0.31V greater than the voltage on
ONLd and it crosses the 1.238V threshold and enables
its LR_ controller about 4ms before ONLd’s controller.
Similarly, the 4μA current through R2 (75kΩ) and the 2μA
current through R3 (150kΩ) cause their LR_ controllers
to each start about 4ms before the next one. Any desired
sequence and delay can be programmed by calculat-
ing the charge rate of C1 and voltage drops across R1
through R3.
Soft-Start
The soft-start function controls the slew rate of the out-
put voltages and reduces inrush currents during startup.
Each regulator (step-down, LR1 to LR5) goes through a
soft-start routine after it is enabled. During soft-start, the
reference voltage for each positive regulator gradually
ramps up from 0V to the internal reference in 32 steps.
The reference voltage of the negative regulator ramps
down from VL to 125mV in 32 steps. The total soft-start
period for each regulator is 1024 clock cycles for 250kHz
switching frequency and 2048 clock cycles for 500kHz
switching frequency.
Reset
The MAX1530/MAX1531 include an open-drain timed
microprocessor supervisor function to ensure proper
startup of digital circuits. The RESET output asserts low
whenever RSTIN is less than the RSTIN trip threshold.
RESET also asserts low when VL is less than the VL
UVLO threshold, EN is low, or the thermal, undervoltage
or overcurrent fault latches are set. RESET enters the
high-impedance state only after RSTIN remains above
the trip threshold for the duration of the reset timeout
period. The state of RESET has no effect on other por-
tions of the IC.
The RSTIN threshold (1.114V typ) is designed to allow
RSTIN to directly connect to any of the MAX1530/
MAX1531s’ feedback input pins, eliminating the need for
an additional resistive divider. Typically, RSTIN is con-
nected to FB or FBL1 to monitor the supply voltage for
digital logic ICs, but it can be used to monitor any desired
output voltage or it can even be used as a general- pur-
pose comparator.
Fault Protection
Undervoltage Protection
After its soft-start is done, if the output of the main step-
down regulator or any of the linear-regulator outputs
(LR1 to LR5) are below 90% of their normal regulation
point, the MAX1530/MAX1531 activate an internal fault
timer. If the fault condition remains continuously for the
entire fault timer duration, the MAX1530/MAX1531 set
the fault latch, shutting down all the regulator outputs.
Undervoltage faults do not turn off VL. Once the fault
condition is removed, cycling the input voltage or apply-
ing a rising edge on SEQ or EN clears the fault latch and
reactivates the device.
Thermal Protection
The thermal protection limits total power dissipation in the
MAX1530/MAX1531. If the junction temperature exceeds
+160°C, a thermal sensor immediately sets the thermal
fault latch, shutting off all the IC’s outputs including VL,
allowing the device to cool down. The only way to clear
the thermal fault latch is to cycle the input voltage after the
device cools down by at least 15°C.
Overcurrent Protection Block (CSH, CSL)
(MAX1531 Only)
The MAX1531 includes an uncommitted overcurrent
protection block that can be used to measure any input
or output current, using a current-sense resistor or other
sense element. If the measured current exceeds the over-
current protection threshold (300mV typ), the MAX1531
immediately sets the undervoltage fault latch, shutting
down all the regulator outputs. Overcurrent faults do not
turn off VL. An internal lowpass filter prevents large cur-
rent transients of short duration (less than 50μs) from set-
ting the latch. Once the overcurrent condition is removed,
cycling the input voltage clears the fault latch and reacti-
vates the device. A rising edge on SEQ or EN also clears
the fault latch.
In Figure 1’s circuit, the overcurrent protection is used
with the LR4 source driver regulator since that regulator
is powered directly from the input supply and has no cur-
rent limit of its own. The current-sense resistor is placed
in series with the input supply, before the linear regulator’s
external PNP pass transistor. CSH and CSL are connect-
ed to the positive and negative sides of the sense resistor.
Design Procedures
Main Step-Down Regulator
Inductor Selection
Three key inductor parameters must be specified: induc-
tance value (L), peak current (I
PEAK
), and DC resistance
(R
DC
). The following equation includes a constant, LIR,
which is the ratio of peak-to-peak inductor ripple current
to DC load current. A higher LIR value allows smaller
inductance, but results in higher losses and higher ripple.
MAX1530/MAX1531 Multiple-Output Power-Supply
Controllers for LCD Monitors
www.maximintegrated.com
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