Datasheet

PIN
NAME FUNCTION
MAX1530
MAX1531
12 12 RESET
Open-Drain Reset Output. RESET asserts low when the monitored voltage is less
than the reset trip threshold. RESET goes to a high-impedance state only after the
monitored voltage remains above the reset trip threshold for the duration of the reset
timeout period. RESET also asserts low when VL is less than the VL undervoltage
lockout threshold, EN is low, or the thermal, overcurrent or undervoltage fault latches
are set.
13
13
COMP
Step-Down Regulator Compensation Input. A pole-zero pair must be added to
compensate the control loop by connecting a series resistor and capacitor from COMP
to AGND. (See the Compensation Design section.)
14 14 FB
Step-Down Regulator Feedback Input. FB regulates at 1.238V nominal. Connect FB
to the center tap of a resistive voltage-divider between the step-down regulator output
and AGND to set the output voltage. Place the divider close to the FB pin.
15 15 ILIM
Step-Down Regulator Current-Limit Control Input. Connect this dual-mode input to VL
to set the current-limit threshold to its default value of 250mV. The overcurrent
comparator compares the voltage across the low-side N-channel MOSFET with
the current-limit threshold. Connect ILIM to the center tap of a resistive voltage-
divider between VL and AGND to adjust the current-limit threshold to other values. In
adjustable mode, the actual current-limit threshold is 1/5th of the voltage at ILIM over
a 0.25V to 3.0V range. The dual- mode threshold for switchover to the 250mV default
value is approximately 3.5V.
16 16 ONL2
Gamma Linear Regulator (LR2) Enable Input. When EN is above its enable threshold,
VL is above its UVLO threshold, and ONL2 is greater than the internal reference, LR2
is enabled. Drive ONL2 with a logic signal or, for automatic sequencing, connect a
capacitor from ONL2 to AGND. If SEQ is high, EN is above its threshold, and VL is
above its UVLO threshold, an internal 2µA (typ) current source charges the capacitor.
Otherwise, an internal switch discharges the capacitor. Connecting various capacitors
to each ONL_ pin allows the programming of the startup sequence.
17 17 ONL3
Gate-On Linear Regulator (LR3) Enable Input. When EN is above its enable threshold,
VL is above its UVLO threshold, and ONL3 is greater than the internal reference, LR3
is enabled. Drive ONL3 with a logic signal or, for automatic sequencing, connect a
capacitor from ONL3 to AGND. If SEQ is high, EN is above its threshold, and VL is
above its UVLO threshold, an internal 2µA (typ) current source charges the capacitor.
Otherwise, an internal switch discharges the capacitor. Connecting various capacitors
to each ONL_ pin allows the programming of the startup sequence.
20 20 PGND Power Ground
21 21 DL
Low-Side Gate Driver Output. DL drives the synchronous rectier of the step-down
regulator. DL swings from PGND to VL. DL remains low until VL rises above the UVLO
threshold.
22 22 LX
Step-Down Regulator Current-Sense Input. The IC’s current-sense amplier inputs
for current-mode control connect to IN and LX. Connect IN and LX directly to the
high-side N- channel MOSFET drain and source, respectively. The low-side current-
limit comparator inputs connect to LX and PGND to sense voltage across a low-side
N-channel MOSFET.
MAX1530/MAX1531 Multiple-Output Power-Supply
Controllers for LCD Monitors
www.maximintegrated.com
Maxim Integrated │ 11
Pin Description (continued)