Datasheet

MAX1513/MAX1514
TFT-LCD Power-Supply Controllers
26 ______________________________________________________________________________________
where V
T
is 26mV at room temperature and I
BIAS
is the
current through the base-to-emitter resistor (R
BE
). Each
of the four linear-regulator controllers is designed for a
different maximum output current, so they have differ-
ent output drive currents and different bias currents
(I
BIAS
). Each controller’s bias current can be found in
the Electrical Characteristics table. The current listed in
the conditions column for the FB_ regulation voltage
specification is the individual controller’s bias current.
The base-to-emitter resistor for each controller should
be chosen to set the correct I
BIAS
:
The output capacitor and the load resistance create the
dominant pole in the system. However, the internal
amplifier delay, the pass transistor’s input capacitance,
and the stray capacitance at the feedback node create
additional poles in the system. The output capacitor’s
ESR generates a zero. For proper operation, use the
following equations to verify the linear regulator is prop-
erly compensated:
1) First, determine the dominant pole set by the linear
regulator’s output capacitor and the load resistor:
The unity-gain crossover of the linear regulator is:
2) The pole created by the internal amplifier delay is
about 1MHz:
3) Next, calculate the pole set by the transistor’s input
capacitance C
IN
, the transistor’s input resistance
R
IN
, and the base-to-emitter pullup resistor:
g
m
is the transconductance of the pass transistor,
and f
T
is the transition frequency. Both parameters
can be found in the transistor’s data sheet. Because
R
BE
is much greater than R
IN
, the above equation
can be simplified:
The equation can be further simplified:
4) Next, calculate the pole set by the linear regulator’s
feedback resistance and the capacitance between
FB_ and GND (including stray capacitance):
where C
FB
is the capacitance between FB_ and
ground, R
UPPER
is the upper resistor of the linear
regulator’s feedback divider, and R
LOWER
is the
lower resistor of the divider.
5) Next, calculate the zero caused by the output
capacitor’s ESR:
where R
ESR
is the equivalent series resistance
of C
OUT_LR
.
6) To ensure stability, choose C
OUT_LR
large enough
so the crossover occurs well before the poles and
zero calculated in steps 2 to 5. The poles in steps 3
and 4 generally occur at several megahertz and
using ceramic capacitors ensures the ESR zero
occurs at several megahertz as well. Placing the
crossover below 500kHz is sufficient to avoid the
amplifier-delay pole and generally works well,
unless unusual component choices or extra capac-
itances move the other poles or zero below 1MHz.
f
CR
POLE ESR
OUT LR ESR
_
_
=
××
1
2π
f
CR R
POLE FB
FB UPPER LOWER
_
||
=
××
()
1
2π
f
f
h
POLE IN
T
FE
_
=
f
CR
POLE IN
IN IN
_
=
××
1
2π
where C
g
f
R
h
g
IN
m
T
IN
FE
m
, , ==
2π
f
CRR
POLE IN
IN BE IN
_
||
=
××
()
1
2π
f MHz
POLE AMP_
≈ 1
fAf
CROSSOVER V LR POLE LR __
=×
f
I
CV
POLE LR
LOAD MAX LR
OUT LR OUT LR
_
()_
__
=
××2π
R
V
I
BE
BE
BIAS
=
A
V
Ih
I
V
VLR
T
BIAS FE
LOAD LR
REF_
_
≈
⎛
⎝
⎜
⎞
⎠
⎟
×+
×
⎛
⎝
⎜
⎞
⎠
⎟
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥
×
4
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