Datasheet

15Maxim Integrated
High-Efficiency, 4A, Step-Down DC-DC
Regulators with Internal Power Switches
MAX15066/MAX15166
Skip Mode Frequency and Output Ripple
In skip mode, the switching frequency (f
SKIP
) and output
ripple voltage (V
OUT_RIPPLE
) shown in Figure 2 are cal-
culated as follows:
t
ON
is the time needed for inductor current to reach SKIP
current limit (0.58A, typ):
SKIP LIMIT
ON
IN OUT
LI
t
VV
−
×
=
−
[1]
t
OFF1
is the time needed for inductor current to reach the
zero current limit (~0A):
SKIP LIMIT
OFF1
OUT
LI
t
V
−
×
=
[2]
During t
ON
and t
OFF1
the output capacitor stores a
charge equal to (see Figure 2):
( )
( )
−

∆ = ×+



− ×+

OUT SKIP LIMIT ON OFF1
LOAD ON OFF1
1
Q I tt
2
I tt
[3]
Combining [1], [2] and [3], and solving for DQ
OUT
:
−
−

×× −



×+

−

∆=
SKIP LIMIT
SKIP LIMIT LOAD
IN OUT OUT
OUT
I
LI I
2
11
VV V
Q
2
During t
OFF2
(= n x t
CK
, number of clock cycles
skipped), the output capacitor loses this charge or can
approximate as:
OUT
OFF2
LOAD
Q
t
I
∆
=
or approximately as:
−
−

=×× +

−


×−


OFF2 SKIP LIMIT
IN OUT OUT
SKIP LIMIT
LOAD
LOAD
11
t LI
VV V
I
I
2
I
Finally, frequency in skip mode is:
SKIP
ON OFF1 OFF2
1
f
tt t
=
++
Output ripple in skip mode is:
( )
( )
OUT RIPPLE COUT RIPPLE ESR RIPPLE
SKIP LIMIT LOAD ON
OUT
ESR,COUT SKIP LIMIT LOAD
VV V
I It
C
RI I
− −−
−
−
= +
−×
= +
×−
To limit output ripple in skip mode, size C
OUT
based on
the above formula accordingly. All formulas above are
valid for I
LOAD
< I
SKIP-LIMIT
.
Compensation Design Guidelines
The devices use a fixed-frequency, peak current-mode
control scheme to provide easy compensation and
fast transient response. The inductor peak current is
monitored on a cycle-by-cycle basis and compared to
the COMP voltage (output of the voltage error ampli-
fier). The regulator’s duty cycle is modulated based on
the inductor’s peak current value. This cycle-by-cycle
control of the inductor current emulates a controlled cur-
rent source. As a result, the inductor’s pole frequency is
shifted beyond the gain bandwidth of the regulator.
System stability is provided with the addition of a simple
series capacitor-resistor from COMP to GND. This pole-
zero combination serves to tailor the desired response of
the closed-loop system.
The basic regulator loop consists of a power modulator
(comprising the regulator’s pulse-width modulator, slope
compensation ramp, control circuitry, MOSFETs, and
inductor), the capacitive output filter and load, an output
feedback divider, and a voltage-loop error amplifier with
its associated compensation circuitry (see Figure 3).
Figure 2. Skip Mode Waveform
I
L
V
OUT
I
SKIP-LIMIT
t
ON
I
LOAD
V
OUT-RIPPLE
t
OFF1
t
OFF2
= n x T
CK