Datasheet

14 Maxim Integrated
High-Efficiency, 4A, Step-Down DC-DC
Regulators with Internal Power Switches
MAX15066/MAX15166
Output-Capacitor Selection
The key selection parameters for the output capacitor
are capacitance, ESR, ESL, and voltage-rating require-
ments. These affect the overall stability, output ripple
voltage, and transient response of the DC-DC converter.
The output ripple occurs due to variations in the charge
stored in the output capacitor, the voltage drop due to
the capacitor’s ESR, and the voltage drop due to the
capacitor’s ESL. Estimate the output-voltage ripple due
to the output capacitance, ESR, and ESL as follows:
RIPPLE RIPPLE(C) RIPPLE(ESR) RIPPLE(ESL)
VV V V=++
where the output ripple due to output capacitance, ESR,
and ESL is:
PP
RIPPLE(C)
OUT SW
RIPPLE(ESR) P P
I
V
8C f
V I ESR
−
−
∆
=
××
=∆×
and V
RIPPLE(ESL)
can be approximated as an inductive
divider from LX to GND:
RIPPLE (ESL) LX IN
ESL ESL
V VV
LL
=×=×
where V
LX
swings from V
IN
to GND.
The peak-to-peak inductor current (DI
P-P
) is:
( )
OUT
IN OUT
IN
PP
SW
V
VV
V
I
Lf
−

−×


∆=
×
When using ceramic capacitors, which generally have
low-ESR, DV
RIPPLE(C)
dominates. When using electro-
lytic capacitors, DV
RIPPLE(ESR)
dominates. Use ceramic
capacitors for low ESR and low ESL at the switching fre-
quency of the converter. The ripple voltage due to ESL is
negligible when using ceramic capacitors.
As a general rule, a smaller inductor ripple current
results in less output ripple voltage. Since inductor
ripple current depends on the inductor value and
input voltage, the output ripple voltage decreases with
larger inductance and increases with higher input volt-
ages. However, the inductor ripple current also impacts
transient-response performance, especially at low V
IN
to
V
OUT
differentials. Low inductor values allow the induc-
tor current to slew faster, replenishing charge removed
from the output filter capacitors by a sudden load step.
Load-transient response also depends on the selected
output capacitance. During a load transient, the output
instantly changes by ESR x ∆I
LOAD
. Before the controller
can respond, the output deviates further, depending on
the inductor and output capacitor values. After a short
time, the controller responds by regulating the output
voltage back to the predetermined value.
Use higher C
OUT
values for applications that require
light-load operation or transition between heavy load and
light load, triggering skip mode, causing output under-
shooting or overshooting. When applying the load, limit
the output undershooting by sizing C
OUT
according to
the following formula:
LOAD
OUT
CO OUT
I
C
3f V
∆
=
×∆
where ∆I
L
OAD
is the total load change, f
CO
is the unity-
gain bandwidth (or zero-crossing frequency), and ∆V
OUT
is the desired output undershooting. When removing the
load and entering skip mode, the device cannot control
output overshooting, since it has no sink current capabil-
ity; see the Skip Mode Frequency and Output Ripple
section to properly size C
OUT
under this circumstance.
A worst-case analysis in sizing the minimum output
capacitance takes the total energy stored in the inductor
into account, as well as the allowable sag/soar (under-
shoot/overshoot) voltage as follows:
( ) ( )
(
)
( )
22
OUT MAX OUT MIN
OUT (MIN)
2
2
FIN SOAR INIT
LI I
C , voltage soar (overshoot)
VV V
×−
=
+−
( ) ( )
(
)
( )
22
OUT MAX OUT MIN
OUT(MIN)
2
2
INIT FIN SAG
LI I
C , voltage sag (undershoot)
V VV
×−
=
−−
where I
OUT(MAX)
and I
OUT(MIN)
are the initial and final
values of the load current during the worst-case load
dump, V
INIT
is the initial voltage prior to the transient,
V
FIN
is the steady-state voltage after the transient,
V
SOAR
is the allowed voltage soar (overshoot) above
V
FIN
, and V
SAG
is the allowable voltage sag below V
FIN
.
The terms (V
FIN
+ V
SOAR
) and (V
FIN
- V
SAG
) represent
the maximum/minimum transient output voltage reached
during the transient, respectively.
Use these equations for initial output-capacitor selection.
Determine final values by testing a prototype or an evalu-
ation circuit under the worst-case conditions.