Datasheet
12 Maxim Integrated
High-Efficiency, 4A, Step-Down DC-DC
Regulators with Internal Power Switches
MAX15066/MAX15166
The devices enter discontinuous mode when load
current (I
LOAD
) and inductor ripple current (DI
L
) are such
that:
IN OUT OUT
L
LOAD LOAD
SW IN
VV V
I
1
I I 0.21A (typ)
2 2 Lf V
−
∆
− = −× × =
×
During skip-mode operation, the devices skip switch
cycles, switching only as needed to service the load.
This reduces the switching frequency and associated
losses in the internal switch, the synchronous rectifier,
and the inductor. In skip mode, to avoid the occasional
switch cycle “bursts” (and reduce power losses), a
fixed on-time is forecasted using a skip current-limit flag
(0.58A, typ). The on-time, even if controlled by COMP,
cannot be lower than the time needed for the inductor
current to reach 0.58A.
Starting into a Prebiased Output
The devices are capable of safely soft-starting into a pre-
biased output without discharging the output capacitor.
Starting up into a prebiased condition, both low-side and
high-side switches remain off to avoid discharging the pre-
biased output. PWM operation starts only when the SS volt-
age crosses the FB voltage. During soft-start, zero crossing
is activated to avoid reverse current in the device.
Enable Input and Power-Good Output
The devices feature independent device enable
control and power-good signals that allow for flexible
power sequencing. The enable input (EN) accepts a
digital input with a 1.9V (typ) threshold. Apply a voltage
exceeding the threshold on EN to enable the regulator,
or connect EN to IN for always-on operations. Power-
good (PGOOD) is an open-drain output that deasserts
(goes high impedance) when V
FB
is above 0.56V (typ),
and asserts low if V
FB
is below 0.545V (typ).
When the EN voltage is higher than 0.7V (typ) and lower
than 1.9V (typ), most of the internal blocks are disabled;
only an internal coarse preregulator, including the EN
accurate comparator, is kept on. An external voltage-
divider from IN to EN to GND can be used to set the
device turn-on threshold.
Programmable Soft-Start (SS)
The devices utilize a soft-start feature to slowly ramp up
the regulated output voltage to reduce input inrush cur-
rent during startup. Connect a capacitor from SS to GND
to set the startup time (see the Setting the Soft-Start Time
section for capacitor selection details).
Internal LDO (V
DD
)
The devices include an internal 5V (typ) LDO. V
DD
is
externally compensated with a minimum 1FF, low-ESR
ceramic capacitor. V
DD
supplies the low-side switch
driver, and the internal control logic. The V
DD
output
current limit is 90mA (typ) and a UVLO circuit inhibits
switching when V
DD
falls below 3.75V (typ).
Error Amplifier
A high gain-error amplifier provides accuracy for the volt-
age feedback loop regulation. Connect the necessary
compensation network between COMP and GND (see
the Compensation Design Guidelines for details). The
error-amplifier transconductance is 1.6mS (typ). COMP
clamp low is set to 0.68V (typ), just below the slope com-
pensation ramp valley, helping COMP to rapidly return to
correct set point during load and line transients.
PWM Comparator
The PWM comparator compares COMP voltage to the
current-derived ramp waveform (LX current to COMP
voltage transconductance value is 9A/V typ). To avoid
instability due to subharmonic oscillations when the duty
cycle is around 50% or higher, a slope compensation
ramp is added to the current-derived ramp waveform.
The compensation ramp (0.667V x 500kHz) for the
MAX15066 and (0.667V x 350kHz) for the MAX15166 is
equivalent to half of the inductor current down slope in
the worst case (load 4A, current ripple 30% and maxi-
mum duty-cycle operation of 90%).
Overcurrent Protection and Hiccup Mode
When the converter output is shorted or the device
is overloaded, the high-side MOSFET current-limit
event (7.7A, typ) turns off the high-side MOSFET and
turns on the low-side MOSFET. In addition, the device
discharges the SS capacitor (C
SS
) for a fixed period of
time (70ns, typ) through the internal SS low-side switch
R
DS-ON
(R
SS
). If the overcurrent condition persists, the
device continues discharging C
SS
until V
SS
drops below
0.606V and a hiccup event is triggered. The regula-
tor softly resets by pulling COMP low, turning off the
high-side and turning on the low-side, until the low-side
zero-crossing current threshold is reached. The high-
side and low-side MOSFETs remain off and COMP is
pulled low for a period equal to 21 times the nominal
soft-start time (blanking time). This is obtained by charg-
ing SS from 0 to 0.606V with a 5FA (typ) current, and
then slowly discharging it back to 0V with a 250nA (typ)
current. After the blanking time has elapsed, the device
attempts to restart. If the overcurrent fault has cleared,
the device resumes normal operation. Otherwise, a new
hiccup event is triggered (see the Output Short-Circuit
Waveform in the Typical Operating Characteristics).