Datasheet

ΔV
BST
such that the available gate-drive voltage is not
significantly degraded (e.g. ΔV
BST
= 100mV to 300mV)
when determining C
BST
.
Use a low-ESR ceramic capacitor as the boost capacitor
with a minimum value of 100nF.
A small-signal diode can be used for the bootstrap circuit
and must have a minimum voltage rating of V
IN
+ 3V
to withstand the maximum BST voltage. The average
forward current of the diode should meet the following
requirement:
I
F
> Q
GATE
x f
SW
where Q
GATE
is the gate charges of the high-side
MOSFET.
Power Dissipation
The maximum power dissipation of the device depends
on the thermal resistance from the die to the ambient
environment and the ambient temperature. The thermal
resistance depends on the device package, PCB copper
area, other thermal mass, and airflow.
The power dissipated into the package (P
T
) depends
on the supply configuration (see the Typical Application
Circuits). Use the following equation to calculate power
dissipation:
P
T
= V
IN
x [Q
G_TOTAL
x f
SW
+ I
Q
]
where I
Q
is the quiescent supply current at the switching
frequency. See the I
IN
vs. Switching Frequency graph in
the Typical Operating Characteristics for the I
Q
.
Use the following equation to estimate the temperature
rise of the die:
T
J
= T
A
+ (P
T
x θ
JA
)
where θ
JA
is the junction-to-ambient thermal impedance
of the package, P
T
is power dissipated in the device, and
T
A
is the ambient temperature. The θ
JA
is 103.7°C/W
for the 16-pin QSOP and 44°C/W for the 16-pin QSOP-
EP package on multilayer boards, with the conditions
specified by the respective JEDEC standards (JESD51-5,
JESD51-7). An accurate estimation of the junction tem-
perature requires a direct measurement of the case
temperature (T
C
) when actual operating conditions sig-
nificantly deviate from those described in the JEDEC
standards. The junction temperature is then:
T
J
= T
C
+ (P
T
x θ
JC
)
Use 37°C/W as θ
JC
thermal impedance for the 16-pin
QSOP package and 6°C/W for the 16-pin QSOP-EP
package. The case-to-ambient thermal impedance (θ
CA
)
is dependent on how well the heat is transferred from the
PCB to the ambient. Use large copper areas to keep the
PCB temperature low.
PCB Layout Guidelines
Careful PCB layout is critical to achieve clean and stable
operation. The switching power stage requires particular
attention. Follow these guidelines for good PCB layout:
1) Place decoupling capacitors as close as possible to
the IC. Connect the power ground plane (connected to
PGND) and signal ground plane (connected to GND)
at one point near the device.
2) Connect input and output capacitors to the power
ground plane; connect all other capacitors to the signal
ground plane.
3) Keep the high-current paths as short and wide as pos-
sible. Keep the path of switching current (C2 to IN and
C2 to PGND) short. Avoid vias in the switching paths.
4) Connect CSP to the drain of the low-side FET using a
Kelvin connection for accurate current-limit sensing.
5) Ensure all feedback connections are short and direct.
Place the feedback resistors as close as possible to
the IC.
6) Route high-speed switching nodes (BST, LX, DH, and
DL) away from sensitive analog areas (RT, FB, COMP,
and LIM).
24V Supply, 3.3V Output Operation
Typical Application Circuit 1 in the Typical Application
Circuits section shows an application circuit that operates
out of 24V and outputs up to 10A at 3.3V. R5 sets the
switching frequency to 350kHz.
Single 4.5V to 5.5V Supply Operation
Typical Application Circuit 2 in the Typical Application
Circuits section shows an application circuit for a single
+4.5V to +5.5V power-supply operation.
Auxiliary 5V Supply Operation
Typical Application Circuit 3 in the Typical Application
Circuits section shows an application circuit for a +24V
supply to drive the external MOSFETs and an auxiliary
+5V supply to power the device
MAX15046 40V, High-Performance, Synchronous
Buck Controller
www.maximintegrated.com
Maxim Integrated │ 19