Datasheet

side of the PCB. Do not make a direct connection of
the exposed pad copper plane to the SGND (pin 10)
underneath the IC. Connect this plane and SGND
together at the return terminal of the V+ bypass
capacitor
2) Isolate the power components and high-current
paths from sensitive analog circuitry.
3) Keep the high-current paths short, especially at the
ground terminals. This practice is essential for sta-
ble, jitter-free operation.
4) Connect SGND and PGND together close to the
return terminals of the V
L
and V+ high-frequency
bypass capacitors near the IC. Do not connect them
together anywhere else.
5) Keep the power traces and load connections short.
This practice is essential for high efficiency. Use
thick copper PCBs to enhance full-load efficiency
and power dissipation capability.
6) Ensure that the feedback connection from FB to
C
OUT
is short and direct.
7) Route high-speed switching nodes (BST/VDD,
SOURCE) away from the sensitive analog areas
(BYPASS, COMP, FB, and OSC). Use internal PCB
layers for SGND as EMI shields to keep radiated
noise away from the IC, feedback dividers, and the
analog bypass capacitors.
Layout Procedure
1) Place the power components (inductor, C
IN
, and
C
OUT
) first, with ground terminals close to each
other. Make all these connections on the top layer
with wide, copper-filled areas (2oz copper recom-
mended).
2) Group the gate-drive components (boost diodes
and capacitors, and V
L
bypass capacitor) together
near the controller IC.
3) Make the ground connections as follows:
a) Create a small-signal ground plane underneath
the IC.
b) Connect this plane to SGND and use this plane
for the ground connection for BYPASS, COMP,
FB, and OSC.
c) Connect SGND and PGND together at the
return terminal of V+ and V
L
bypass capacitors
near the IC. Make this the only connection
between SGND and PGND.
MAX15036/MAX15037
2.2MHz, 3A Buck or Boost Converters
with an Integrated High-Side Switch
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