Datasheet

+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
MAX148/MAX149
15
delay and maximum sample rate. In external compensa-
tion mode, power-up time is 20ms with a 4.7FF com-
pensation capacitor when the capacitor is initially fully
discharged. From fast power-down, startup time can be
eliminated by using low-leakage capacitors that do not
discharge more than ½ LSB while shut down. In power-
down, leakage currents at V
REF
cause droop on the
reference bypass capacitor. Figures 12a and 12b show
the various power-down sequences in both external and
internal clock modes.
Figure 11a. External Clock Mode, 15 Clocks/Conversion Timing
Figure 11b. External Clock Mode, 16 Clocks/Conversion Timing
Figure 12a. Timing Diagram Power-Down Modes, External Clock
SCLK
DIN
DOUT
CS
S CONTROL BYTE 0 CONTROL BYTE 1S
CONVERSION RESULT 0
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0
CONVERSION RESULT 1
SSTRB
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0
CONTROL BYTE 2S
1
8 115 158 1
SCLK
DIN
DOUT
CS
S
1 8 16
1 8 16
CONTROL BYTE 0 CONTROL BYTE 1S
CONVERSION RESULT 0
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0 B9 B8 B7 B6
CONVERSION RESULT 1
10 + 2 DATA BITS 10 + 2 DATA BITS INVALID
DATA
VALID
DATA
EXTERNAL
EXTERNAL
S X X X X X 1 1 S 0 0X XXXX X X X X XS 1 1
SOFTWARE
POWER-DOWN
MODE
DOUT
DIN
CLOCK
MODE
SHDN
SETS EXTERNAL
CLOCK MODE
SETS EXTERNAL
CLOCK MODE
SETS SOFTWARE
POWER-DOWN
POWERED UP POWERED UP
HARDWARE
POWER-DOWN
POWERED UP