Datasheet

+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
MAX148/MAX149
12
Figure 7. Detailed Serial-Interface Timing
Figure 8. External Clock Mode SSTRB Detailed Timing
The T/H acquires the input signal as the last three bits of
the control byte are clocked into DIN. Bits PD1 and PD0
of the control byte program the clock mode. Figures 7–10
show the timing characteristics common to both modes.
External Clock
In external clock mode, the external clock not only shifts
data in and out, but it also drives the analog-to-digital
conversion steps. SSTRB pulses high for one clock period
after the last bit of the control byte. Successive- approxi-
mation bit decisions are made and appear at DOUT on
each of the next 12 SCLK falling edges (Figure 6). SSTRB
and DOUT go into a high-impedance state when CS goes
high; after the next CS falling edge, SSTRB outputs a
logic-low. Figure 8 shows the SSTRB timing in external
clock mode.
The conversion must complete in some minimum time, or
droop on the sample-and-hold capacitors may degrade
conversion results. Use internal clock mode if the serial-
clock frequency is less than 100kHz, or if serial-clock
interruptions could cause the conversion interval to
exceed 120Fs.
t
DO
SCLK
DIN
DOUT
CS
t
CSS
t
DS
t
DH
t
DV
t
TR
t
CSH
t
CL
t
CH
t
CSH
PD0 CLOCKED IN
SCLK
t
SSTRB
SSRTB
CS
t
SDV
t
STR
t
SSTRB