Datasheet

5Maxim Integrated
MAX14920/MAX14921
High-Accuracy 12-/16-Cell Measurement AFEs
DC ELECTRICAL CHARACTERISTICS (continued)
(V
P
= +65V, DGND = AGND, V
L
= V
EN
= +3.3V, V
A
= +5V, C
SAMPLE
= 1FF, T
A
= -40°C to +85°C, unless otherwise noted. Typical
values are at T
A
= +25°C.) (Note 2)
Note 2: All devices are 100% production tested at T
A
= +25°C. Limits over the operating temperature range are guaranteed by design.
Note 3: Where n = 1–12 (MAX14920) and n = 1–16 (MAX14921).
Note 4: Output error V
O_ERR
is the difference between the input cell difference voltage (V
D
= V
CV(n)
- V
CV(n - 1)
) and the
output voltage V
AOUT
. Where n = 1–12 (MAX14920) and n = 1–16 (MAX14921). Output error depends on buffer ampli-
fier errors and parasitic capacitance charge injection error. Since parasitic capacitance error is PCB dependent, output
error is guaranteed by design for a sampling capacitor of 1FF and parasitic capacitance less than 2.5pF on CTn (see the
Measurement Accuracy section for a detailed explanation).
Note 5: Buffer amplifier self-calibrates its offset at power-up and every time it is requested. Due to possible thermal drift after
power-up phase, it is suggested to run self-calibration on a regular basis to get best performance
(see the Buffer Amplifier Offset Calibration section for a detailed explanation).
Note 6: Amplifier error is the sum of all errors including amplifier offset and gain error.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Level-Shifting Delay Time t
LS_DELAY
Delay from SMPLB set to 1 or SAMPL
falling edge to shifting of all cell voltages
to ground and available for reading
25 50
Fs
AOUT Voltage-Droop Time t
DROOP
Droop to -1mV (Figure 2) 1 ms
T_ Settling Time t
TS
Measured between T_ input selection
and AOUT settling to +1mV accuracy,
C
LOAD
= 100pF, SC2 = 1
5
Fs
T_ Turn-On Delay Time t
TD
0.2
Fs
V
P
Settling Time t
VPS
Measured between V
P
/12 (MAX14920),
V
P
/16 (MAX14921) input selection and
AOUT, settling to 2.5%,
C
LOAD
= 100pF, SC3 = 1
25 60
Fs
Self-Calibration Time 8 ms
THERMAL DETECTION
Thermal Shutdown +140 °C
Thermal-Shutdown Hysteresis 15 °C
SPI TIMINGS (Figure 3)
SDI to SCLK Setup t
DS
50 ns
SDI to SCLK Hold t
DH
12 ns
SCLK to SDO Valid t
DO
100 ns
CS Fall to SDO Enable
t
DV
100 ns
CS Rise to SDO Disable
t
TR
80 ns
CS Pulse Width
t
CSW
50 ns
CS Fall to SCLK Rise Setup
t
CSS
100 ns
CS Rise to SCLK Rise Hold
t
CSH
0 ns
SCLK High Pulse Width t
CH
65 ns
SCLK Low Pulse Width t
CL
65 ns
SCLK Period t
CP
208 ns