Datasheet

23Maxim Integrated
MAX14920/MAX14921
High-Accuracy 12-/16-Cell Measurement AFEs
Shorts between cell connections can be detected during
normal operation. The cell readout voltage results in ~0V
or ~V
A
depending on where the short happens. In the
case of shorts, the maximum currents flowing in/out of the
pins must be limited and overvoltages avoided, including
the external components (balancing FETs and sampling
capacitors).
Open-wire conditions between the CV_ inputs and the
cells can be detected in two different ways:
The first method of open-wire detection:
Set the DIAG bit to 1 while in the sampling phase. This
applies a leakage current of 10FA to the CVn inputs. If
CVn is unconnected, the leakage current starts discharg-
ing the sampling capacitor with a slew rate of I
LEAK
/
C
SAMLPE
(~10FA/1FF = 100mV/10ms) down to CVn - 1.
Two successive readouts show considerable cell voltage
change in case of an open wire. Alternatively, waiting for
a sampling time of ~300ms to 500ms reduces the cell
voltage to below the UV_VC
VTH
threshold voltage.
First open-wire detection procedure:
• Set DIAG bit to 1
• Wait > 0.5s before hold phase
• Read out the Cn bit or the CVn voltage under SPI
control, where n = 1–12 (MAX14920) and n = 1–16
(MAX14921)
The second method of open-wire detection:
To check for a single open-wire connection, it is faster to
enable the balancing FET only on the selected cell during
the sampling phase and then reading out the selected
cell voltage. If CVn is unconnected, the balancing FET
rapidly (time depends on the balancing resistance used)
shorts CVn to CVn - 1 and the readout phase shows ~0V
or CVn and a voltage higher than V
A
on CVn + 1.
Second open-wire detection procedure:
• Set the BAn bit to 1
• Wait for a time of R
BAL
x C
SAMPLE
before switching
to the hold phase
• Route the CVn voltage to AOUT
• Repeat this procedure for all cells
During this procedure, the capacitors and external FETs
need to withstand a voltage equal to V
CVn
- V
CVn-1
,
where n = 1–12 (MAX14920) and n = 1–16 (MAX14921).
Input-Voltage Clamping
The devices have internal ESD-protection diodes that can
clamp input voltage lower than AGND or higher than V
P
(CVn where n is > 1) or 6 volts for (CV1) during a fault con-
dition. Connect series resistors (R
LIM
) to the inputs to limit
the currents flowing through the forward-biased diodes
during fault conditions (Figure 10). Choose current-limiting
resistors so the input currents are limited to I
CV_
(max) =
10mA. The additional power dissipation due to the fault
currents needs to be calculated when a voltage-clamping
condition occurs on another channel that is not being
measured. Sampling capacitors and balancing FETs must
be chosen appropriately or protected with external voltage
clamps to survive such events.
Power Sequencing
The V
A
and V
L
supplies can be applied at any sequence
with respect to each other and also independently of the
V
P
and supplies CV_ inputs. The V
P
voltage has to con-
nect to the highest voltage of the cell stack.
Figure 10. Input-Voltage Clamp
CTn*
C
SAMPLE
V
P
CVn*
CVn*- 1
R
LIM
R
LIM
BAn*
R
BAL
CBn*
AGNDCV0
*n = 1–12 (MAX14920) AND n = 1–16 (MAX14921)
BA1
CV1
MAX14920
MAX14921