Datasheet
21Maxim Integrated
MAX14920/MAX14921
High-Accuracy 12-/16-Cell Measurement AFEs
SPI Monitoring Bits
The monitoring bits provide feedback of undervoltage
conditions and thermal shutdown, as well as indication
when the devices are ready for operation after power-up.
Table 4 describes the diagnostics/monitoring bits that
the devices send back to the host controller through the
SDO output.
Flexible Logic Interface
The serial/parallel logic control interface logic levels can
be defined to be in a range between +1.62V (min) and
+5.5V (max). The voltage applied to the V
L
pin defines
the logic levels. Choose the V
L
voltage to match the con-
troller and ADC’s I/O logic levels.
Table 4. SPI Monitoring Bits
*Not available on the MAX14920. Setting the bit to 0 or 1 does not affect the operating of the MAX14920.
NAME BITS ACCESS DESCRIPTION
C1 0 R 1: During hold phase if cell 1 voltage is below UV_V
CVTH or above VA
C2 1 R 1: During hold phase if cell 2 voltage is below UV_VCVTH or above VA
C3 2 R 1: During hold phase if cell 3 voltage is below UV_VCVTH or above VA
C4 3 R 1: During hold phase if cell 4 voltage is below UV_VCVTH or above VA
C5 4 R 1: During hold phase if cell 5 voltage is below UV_VCVTH or above VA
C6 5 R 1: During hold phase if cell 6 voltage is below UV_VCVTH or above VA
C7 6 R 1: During hold phase if cell 7 voltage is below UV_VCVTH or above VA
C8 7 R 1: During hold phase if cell 8 voltage is below UV_VCVTH or above VA
C9 8 R 1: During hold phase if cell 9 voltage is below UV_VCVTH or above VA
C10 9 R 1: During hold phase if cell 10 voltage is below UV_VCVTH or above VA
C11 10 R 1: During hold phase if cell 11 voltage is below UV_VCVTH or above VA
C12* 11 R 1: During hold phase if cell 12 voltage is below UV_VCVTH or above VA
C13* 12 R 1: During hold phase if cell 13 voltage is below UV_VCVTH or above VA
C14* 13 R 1: During hold phase if cell 14 voltage is below UV_VCVTH or above VA
C15* 14 R 1: During hold phase if cell 15 voltage is below UV_VCVTH or above VA
C16* 15 R 1: During hold phase if cell 16 voltage is below UV_VCVTH or above VA
OP0 16 R
Product identifying bits
MAX14921 (OP0 = 0, OP1 = 0)
MAX14920 (OP0 = 1, OP1 = 0)
OP1 17 R
REV0 18 R
Die version
MAX14920/MAX14921 version bits
REV1 19 R
UV_VA
20 R 1: VA is below UV_VAVTH
UV_VP 21 R 1: V
P is below UV_VPVTH. If LOPW = 1, VP UVLO circuit is disabled and this bit is always set to 1
RDY
22 R
1: Device is not ready to operate (power-up phase or buffer amplifier is in self-calibration
procedure)
OT 23 R 1: Device is in thermal shutdown