Datasheet

19Maxim Integrated
MAX14920/MAX14921
High-Accuracy 12-/16-Cell Measurement AFEs
Table 1. SPI Configuration/Control Bits (continued)
*Not available on the MAX14920. Setting the bit to 0 or 1 does not affect the operating of the MAX14920.
**For the MAX14920, if n > 12, V
AOUT
= 0V.
NAME BITS ACCESS RESET DESCRIPTION
CB9 8 R/W 0
0: Set BA9 output low
1: Set BA9 output high
CB10 9 R/W 0
0: Set BA10 output low
1: Set BA10 output high
CB11 10 R/W 0
0: Set BA11 output low
1: Set BA11 output high
CB12* 11 R/W 0
0: Set BA12 output low
1: Set BA12 output high
CB13* 12 R/W 0
0: Set BA13 output low
1: Set BA13 output high
CB14* 13 R/W 0
0: Set BA14 output low
1: Set BA14 output high
CB15* 14 R/W 0
0: Set BA15 output low
1: Set BA15 output high
CB16* 15 R/W 0
0: Set BA16 output low
1: Set BA16 output high
ECS 16 R/W 0
0: Cell selection is disabled
1: Cell selection is enabled
SC0 17 R/W 0
[ECS, SC0, SC1, SC2, SC3]
1 – SC0, SC1, SC2, SC3: Selects the cell for voltage readout during hold phase.**
The selected cell voltage is routed to AOUT after the rising CS edge. See Table 2.
0 – 0, 0, 0, 0: AOUT is three-stated and sampling switches are configured for
parasitic capacitance error calibration.
0 – 1, 0, 0, 0: AOUT is three-statedand self-calibration of buffer amplifier offset
voltage is initiated after the following rising CS.
0 – SC0, SC1, 0, 1: Switches the T1, T2. T2 analog inputs directly to AOUT. See
Table 3.
0 – 0, 0, 1, 1: V
P/12 (MAX14920) or VP/16 (MAX14921) voltage is routed to AOUT
on the next rising CS
0 – SC0, SC1, 1, 1: Routes and buffers the T1, T2. T3 to AOUT. See Table 3.
SC1 18 R/W 0
SC2 19 R/W 0
SC3 20 R/W 0
SMPLB
21 R/W 0
0: Device in sample phase if SAMPL input is logic-high
1: Device in hold phase
DIAG 22 R/W 0
0: Normal operation
1: Diagnostic enable, 10FA leakage is sunk on all CV_ inputs (CV0–CV16).
LOPW 23 R/W 0
0: Normal operation
1: Low-power mode enabled. Current into LDOIN is reduced to 125FA. Current
into V
P is reduced to 1FA.