Datasheet

18Maxim Integrated
MAX14920/MAX14921
High-Accuracy 12-/16-Cell Measurement AFEs
Figure 7. SPI Serial Interface Bits
read out the total cell stack voltage, set the [ECS, SC0,
SC1, SC2, SC3] bits to [0, 0, 0, 1, 1]. The total cell stack
voltage can be read during the sample or hold phase.
SPI Serial Interface
Control of the devices is done through a 24-bit SPI inter-
face. The controller sends the serial data to the devices
through the SDI input. The devices simultaneously send
out monitoring data at the SDO output. This scheme
allows daisy-chained operation with other daisy-chain-
able devices, such as ADC converters. Figure 7 shows
the serial bit sequence.
CB1 is the first bit expected from the controller and C1 is
the first bit that the devices sent to the controller. The SDO
data changes on the falling edge of the SCLK signals. The
devices sample the SDI data on the rising edge of SCLK.
SPI Configuration/Control Bits
The configuration/control bits allow enabling of the
charge-balance switches, sampling and holding of all
the cell voltages, selecting the cell for voltage output,
selecting the T_ input channels, and enabling diagnos-
tics mode. Table 1 describes the bits that the devices
receive from the host controller for configuration and
control through SDI.
Table 1. SPI Configuration/Control Bits
NAME BITS ACCESS RESET DESCRIPTION
CB1 0 W 0
0: Set BA1 output low
1: Set BA1 output high
CB2 1 W 0
0: Set BA2 output low
1: Set BA2 output high
CB3 2 W 0
0: Set BA3 output low
1: Set BA3 output high
CB4 3 W 0
0: Set BA4 output low
1: Set BA4 output high
CB5 4 W 0
0: Set BA5 output low
1: Set BA5 output high
CB6 5 W 0
0: Set BA6 output low
1: Set BA6 output high
CB7 6 W 0
0: Set BA7 output low
1: Set BA7 output high
CB8 7 W 0
0: Set BA8 output low
1: Set BA8 output high
SCLK
SDI
SDO
CB1 SMPLB LOPWCB2CB3 CB4CB5 CB6CB7 CB8CB9 CB10 CB11 CB12 CB13 CB14 CB15 CB16 ECSSC0 SC1SC2 SC3DIA
GX
X
C1 UV_V
AO
TC2 C3 C4 C5 C6 C7 C8 C9 C10C11 C12C13 C14C15 C16OP0 OP 1REV 0REV 1UV_VP RDY X
CS