Datasheet

13Maxim Integrated
MAX14920/MAX14921
High-Accuracy 12-/16-Cell Measurement AFEs
Pin Description (continued)
PIN
NAME FUNCTION
MAX14920
(64 TQFP-EP)
MAX14921
(80 TQFP)
51 67 CV3
Cell Voltage Input 3. Connect CV3 to cell anode/cathode. Connect CV3 to the
highest voltage of the battery cell stack if not used.
52 68 BA3
Cell-Balancing Gate Driver Output 3. Connect BA3 to the gate of the external
n-channel FET. Leave BA3 unconnected if not used.
53 69 CT3
Sampling Capacitor 3 High Terminal. CT3 internally connects to CV3 when
SAMPL is logic-high. Connect a 1FF capacitor between CT3 and CB3. Leave CT3
unconnected if not used.
54 70 CB3
Sampling Capacitor 3 Low Terminal. CB3 internally connects to CV2 when
SAMPL is logic-high. Connect a 1FF capacitor between CT3 and CB3. Leave CB3
unconnected if not used.
55 71 CV2
Cell Voltage Input 2. Connect CV2 to cell anode/cathode. Connect CV2 to the
highest voltage of the battery cell stack if not used.
56 72 BA2
Cell-Balancing Gate Driver Output 2. Connect BA2 to the gate of the external
n-channel FET. Leave BA2 unconnected if not used.
57 73 CT2
Sampling Capacitor 2 High Terminal. CT2 internally connects to CV2 when
SAMPL is logic-high. Connect a 1FF capacitor between CT2 and CB2. Leave CT2
unconnected if not used.
58 74 CB2
Sampling Capacitor 2 Low Terminal. CB2 internally connects to CV1 when
SAMPL is logic-high. Connect a 1FF capacitor between CT2 and CB2. Leave CB2
unconnected if not used.
59 75 CV1 Cell Voltage Input 1. Connect CV1 to cell anode/cathode.
60 76 BA1
Cell-Balancing Gate Driver Output 1. Connect BA1 to the gate of the external
n-channel FET. Leave BA1 unconnected if not used.
61 77 CT1
Sampling Capacitor Connection 1 High Terminal. CT1 internally connects to CV1
when SAMPL is logic-high. Connect a 1FF capacitor between CT1 and CV0.
Leave CT1 unconnected if not used.
62 78 CV0 Cell Voltage Input 0. Connect CV0 to AGND.
63 79 EN
Enable Input. Drive EN low to put the device into shutdown mode and reset the SPI
registers. The +5V LDO remains active in the shutdown mode. Drive EN high for
normal operation.
64 80
CS
SPI Chip-Select Input. Active low.
15 CV16
Cell Voltage Input 16. Connect CV16 to cell anode/cathode. Connect CV16 to the
highest voltage of the battery cell stack if not used.
16 BA16
Cell-Balancing Gate Driver Output 16. Connect BA16 to the gate of the external
n-channel FET. Leave BA16 unconnected if not used.
17 CT16
Sampling Capacitor Connection 16 High Terminal. CT16 internally connects to
CV16 when SAMPL is logic-high. Connect a1FF capacitor between CT16 and CB16.
Leave CT16 unconnected if not used.