Datasheet

12Maxim Integrated
MAX14920/MAX14921
High-Accuracy 12-/16-Cell Measurement AFEs
Pin Description (continued)
PIN
NAME FUNCTION
MAX14920
(64 TQFP-EP)
MAX14921
(80 TQFP)
36 52 BA7
Cell-Balancing Gate Driver Output 7. Connect BA7 to the gate of the external
n-channel FET. Leave BA7 unconnected if not used.
37 53 CT7
Sampling Capacitor 7 High Terminal. CT7 internally connects to CV7 when
SAMPL is logic-high. Connect a 1FF capacitor between CT7 and CB7. Leave CT7
unconnected if not used.
38 54 CB7
Sampling Capacitor 7 Low Terminal. CB7 internally connects to CV6 when
SAMPL is logic-high. Connect a 1FF capacitor between CT7 and CB7. Leave CB7
unconnected if not used.
39 55 CV6
Cell Voltage Input 6. Connect CV6 to cell anode/cathode. Connect CV6 to the
highest voltage of the battery cell stack if not used.
40 56 BA6
Cell-Balancing Gate Driver Output 6. Connect BA6 to the gate of the external
n-channel FET. Leave BA6 unconnected if not used.
41 57 CT6
Sampling Capacitor 6 High Terminal. CT6 internally connects to CV6 when
SAMPL is logic-high. Connect a 1FF capacitor between CT6 and CB6. Leave CT6
unconnected if not used.
42 58 CB6
Sampling Capacitor 6 Low Terminal. CB6 internally connects to CV7 when
SAMPL is logic-high. Connect a 1FF capacitor between CT6 and CB6. Leave CB6
unconnected if not used.
43 59 CV5
Cell Voltage Input 5. Connect CV5 to cell anode/cathode. Connect CV5 to the
highest voltage of the battery cell stack if not used.
44 60 BA5
Cell-Balancing Gate Driver Output 5. Connect BA5 to the gate of the external
n-channel FET. Leave BA5 unconnected if not used.
45 61 CT5
Sampling Capacitor 5 High Terminal. CT5 internally connects to CV5 when
SAMPL is logic-high. Connect a 1FF capacitor between CT5 and CB5. Leave CT5
unconnected if not used.
46 62 CB5
Sampling Capacitor 5 Low Terminal. CB5 internally connects to CV4 when
SAMPL is logic-high. Connect a 1FF capacitor between CT5 and CB5. Leave CB5
unconnected if not used.
47 63 CV4
Cell Voltage Input 4. Connect CV4 to cell anode/cathode. Connect CV4 to the
highest voltage of the battery cell stack if not used.
48 64 BA4
Cell-Balancing Gate Driver Output 4. Connect BA4 to the gate of the external
n-channel FET. Leave BA4 unconnected if not used.
49 65 CT4
Sampling Capacitor 4 High Terminal. CT4 internally connects to CV4 when
SAMPL is logic-high. Connect a 1FF capacitor between CT4 and CB4. Leave CT4
unconnected if not used.
50 66 CB4
Sampling Capacitor 4 Low Terminal. CB4 internally connects to CV3 when
SAMPL is logic-high. Connect a 1FF capacitor between CT4 and CB4. Leave CB4
unconnected if not used.