Datasheet

10Maxim Integrated
MAX14920/MAX14921
High-Accuracy 12-/16-Cell Measurement AFEs
Pin Description
PIN
NAME FUNCTION
MAX14920
(64 TQFP-EP)
MAX14921
(80 TQFP)
1 1 SCLK SPI Clock Input
2 2 SDI SPI Data Line Input
3 3 SDO SPI Data Line Output
4 4 SAMPL
Sample Control Input. Voltages at CV_ inputs are tracked when SAMPL is logic-
high. When SAMPL transitions from high to low, the differential voltages on CV_ are
held internally and made ready for readout at the AOUT output.
5 5 V
L
Logic Supply Input. Bypass V
L
to DGND with a 0.1FF capacitor as close as
possible to the device.
6 6 DGND Digital Ground
7 7 T3
Single-Ended Voltage Input. T3 can be connected to a temperature sensor or other
analog voltage.
8 8 T2
Single-Ended Voltage Input. T2 can be connected to a temperature sensor or other
analog voltage.
9 9 T1
Single-Ended Voltage Input. T1 can be connected to a temperature sensor or other
analog voltage.
10 10 AOUT Buffered Amplifier Output
11 11 AGND
Analog Ground. AGND is a low-noise ground. Connect CV0 to AGND. Connect
DGND to AGND.
12 12 V
A
+5V LDO Output. Bypass V
A
to AGND with a 1FF capacitor as close as possible to
the device.
13 13 LDOIN
+5V LDO Power Supply. Connect LDOIN to V
P
to enable the LDO. Connect LDOIN
to V
A
to disable the LDO and use an external +5V supply.
14 14 V
P
Power Supply. Connect to the highest voltage of the battery cell stack. Bypass V
P
to
AGND with a 0.1FF capacitor as close as possible to the device.
15 31 CV12
Cell Voltage Input 12. Connect CV12 to cell anode/cathode. Connect CV12 to the
highest voltage of the battery cell stack if not used.
16 32 BA12
Cell-Balancing Gate Driver Output 12. Connect BA12 to the gate of the external
n-channel FET. Leave BA12 unconnected if not used.
17 33 CT12
Sampling Capacitor 12 High Terminal. CT12 internally connects to CV12 when
SAMPL is logic-high. Connect a 1FF capacitor between CT12 and CB12. Leave
CT12 unconnected if not used.
18 34 CB12
Sampling Capacitor 12 Low Terminal. CB12 internally connects to CV11 when
SAMPL is logic-high. Connect a 1FF capacitor between CT12 and CB12. Leave
CB12 unconnected if not used.
19 35 CV11
Cell Voltage Input 11. Connect CV11 to cell anode/cathode. Connect CV12 to the
highest voltage of the battery cell stack if not used.
20 36 BA11
Cell-Balancing Gate Driver Output 11. Connect BA11 to the gate of the external
n-channel FET. Leave BA11 unconnected if not used.