Datasheet

54 Maxim Integrated
Quad Serial UART with 128-Word FIFOs
MAX14830
GloblComnd—Global Command Register
Bits 7–0: GlbCom[n]
The GloblComnd register is the only global write register in the MAX14830. Every byte written to GloblComnd is sent
simultaneously to all four UARTs. Every byte sent by the SPI/I
2
C master to location 0x1F is interpreted as a global com-
mand by all the four internal UARTs.
The MAX14830 logic supports the following commands (Table 8):
 •GlobalTxSynchronization
 •ExtendedAddressingSpaceEnable(togetaccesstoregistersbeyondaddress0x1F)
 •ExtendedAddressingSpaceDisable(todisableaccesstoregistersbeyondaddress0x1F)
The last two commands (0xCE/0xCD) enable/disable the access to registers in the extended space of the register map
when MAX14830 operates in SPI mode. The SPI command byte has only 5 bits to address a given register so that the
registers beyond 0x1F could not be addressed using the standard access method.
In I
2
C mode, there is no need to explicitly enable and disable the extended register map access as I
2
C allows up to
7 bits for register addressing.
To extend the addressing capability of the SPI command byte, send a 0xCE to location 0x1F. The internal SPI address
is generated as 0010 A3A2A1A0, where A3A2A1A0 is the least significant nibble of the command byte. Bit A4 of the
command byte is disregarded when the extended space of the register map is enabled and only the least significant
nibble is used for addressing purposes (Table 9).
Bits U1 and U0 of the command byte maintain their meaning in the extended mode. See the SPI Interface section for
more information.
To return to standard addressing mode, the SPI master has to send the 0xCD command. In this case, the internal SPI
address is generated as follows (default): 000A4 A3A2A1A0
Table 8. GloblComnd Command Descriptions
Table 9. Extended Mode Addressing
(SPI only)
GloblComnd[7:0] COMMAND DESCRIPTION
0xE0 Tx Command 0
0xE1 Tx Command 1
0xE2 Tx Command 2
0xE3 Tx Command 3
0xE4 Tx Command 4
0xE5 Tx Command 5
0xE6 Tx Command 6
0xE7 Tx Command 7
0xE8 Tx Command 8
0xE9 Tx Command 9
0xEA Tx Command 10
0xEB Tx Command 11
0xEC Tx Command 12
0xED Tx Command 13
0xEE Tx Command 14
REGISTER
SPI MODE
ADDRESS
I
2
C MODE
ADDRESS
TxSynch 0x00 0x20
SynchDelay1 0x01 0x21
SynchDelay2 0x02 0x22
TIMER1 0x03 0x23
TIMER2 0x04 0x24
RevID 0x05 0x25
ADDRESS: 0x1F
MODE: W
BIT 7 6 5 4 3 2 1 0
NAME
GlbCo
m7
GlbCom6 GlbCom5 GlbCom4 GlbCom3 GlbCom2 GlbCom1 GlbCom0
GloblComnd[7:0] COMMAND DESCRIPTION
0xEF Tx Command 15
0xCE Enable extended register map access
0xCD Disable extended register map access