Datasheet

51Maxim Integrated
Quad Serial UART with 128-Word FIFOs
MAX14830
PLLConfig—PLL Configuration Register
Bits 7, 6: PLLFactor[n]
The PLLFactor[n] bits allow programming the PLL multiplication factors. The input and output frequencies of the PLL
have to be limited to the ranges shown in Table 7. Enable the PLL through CLKSource[2].
Bits 5–0: PreDiv[n]
The PreDiv[n] bits allow programming the divisor of the PLL’s predivider. The divisor must be chosen so that the output
frequency of the predivider, which equals the PLL’s input frequency, is limited to the ranges shown in Table 4. The
input frequency of XIN, is f
CLK
:
f
PLLIN
= f
CLK
/PreDiv
See Figure 17. PreDiv is an integer that must be in the range of 1 to 63.
Figure 17. PLL Signal Path
Table 7. PLLFactor_ Selector Guide
ADDRESS: 0x1A
MODE: R/W
BIT 7 6 5 4 3 2 1 0
NAME
PLLFactor1 PLLFactor0 PreDiv5 PreDiv4 PreDiv3 PreDiv2 PreDiv1 PreDiv0
RESET
0 0 0 0 0 0 0 1
f
CLK
f
PLL IN
PLL
PRE-DIVIDER
f
REF
FRACTIONAL
BAUD-RATE
GENERATORS
PLLFactor1 PLLFactor0 MULTIPLICATION FACTOR
f
PLLIN
f
REF
MIN MAX MIN MAX
0 0 6 500kHz 800kHz 3MHz 4.8MHz
0 1 48 850kHz 1.2MHz 40.8MHz 56MHz
1 0 96 425kHz 1MHz 40.8MHz 96MHz
1 1 144 390kHz 667kHz 56MHz 96MHz