Datasheet
45Maxim Integrated
Quad Serial UART with 128-Word FIFOs
MAX14830
TxFIFOLvl—Transmit FIFO Level Register
Bits 7–0: TxFL[n]
The TxFIFOLvl register represents the current number of words in the Transmit FIFO.
RxFIFOLvl—Receive FIFO Level Register
Bits 7–0: RxFL[n]
The RxFIFOLvl Level register represents the current number of words in the Receive FIFO.
FlowCtrl—Flow Control Register
Bits 7–4: SwFlow[n]
The SwFlow[n] bits configure auto software flow control and/or special character detection in combination with the
characters defined in the XON1, XON2, XOFF1, and/or XOFF2 registers. See Table 4.
FlowCtrl[n] select which of the XON1, XON2, XOFF1, or/and XOFF2 characters are used for special character detec-
tion and/or auto flow control. If auto receiver flow control is enabled through SwFlowEn and FlowCtrl[n], the XON and
XOFF characters that the MAX14830 receives are filtered out and are not put into the RxFIFO. Set the SwFlowEn bit to
0 and set MODE2[4] to 1 to enable special character detection. Under these conditions, auto flow transmit flow control
is not used.
If both special character detection (MODE2[4]) and automatic software flow control (FlowCtrl[3]) are to be enabled,
XON1 and XOFF1 define the auto flow control characters while XON2 and XOFF2 define the special character detec-
tion characters.
Bit 3: SwFlowEn
The SwFlowEn bit enables automatic software flow control. The characters used for automatic software flow control are
selected in FlowCtrl[n]. If special character detection (MODE2[4] = 1) is used in addition to automatic software flow
control, XON1 and XOFF1 are used for flow control, while XON2 and XOFF2 define the special characters.
ADDRESS: 0x11
MODE: R
BIT 7 6 5 4 3 2 1 0
NAME
TxFL7 TxFL6 TxFL5 TxFL4 TxFL3 TxFL2 TxFL1 TxFL0
RESET
0 0 0 0 0 0 0 0
ADDRESS: 0x12
MODE: R
BIT 7 6 5 4 3 2 1 0
NAME
RxFL7 RxFL6 RxFL5 RxFL4 RxFL3 RxFL2 RxFL1 RxFL0
RESET
0 0 0 0 0 0 0 0
ADDRESS: 0x13
MODE: R/W
BIT 7 6 5 4 3 2 1 0
NAME
SwFlow3 SwFlow2 SwFlow1 SwFlow0 SwFlowEn GPIAddr AutoCTS AutoRTS
RESET
0 0 0 0 0 0 0 0