Datasheet

44 Maxim Integrated
Quad Serial UART with 128-Word FIFOs
MAX14830
FlowLvl—Flow Level Register
FlowLvl is used for selecting the RxFIFO threshold levels used for software (XON/XOFF) and hardware (RTS/CTS) flow
control.
Bits 7–4: Resume[n]
Resume[n] bits set the Transmit FIFO threshold at which an XON is automatically sent or RTS_ is automatically set low.
This signals the far end station to start transmission. The actual threshold level is calculated as 8 x Resume[n]. The
resulting level is in the range of 0 to 120.
Bits 3–0: Halt[n]
Halt[n] bits set a Receive FIFO threshold level at which an XOFF is automatically sent or RTS_ is automatically set high,
depending on whether automatic software or hardware flow control is enabled. This signals the far end station to halt
transmission. The actual threshold level is calculated as 8 x Halt[n]. Hence the selectable threshold granularity is eight.
The resulting level is in the range of 0 to 120.
FIFOTrigLvl—FIFO Interrupt Trigger Level Register
Bits 7–4: RxTrig[n]
The RxTrig[n] bits allow definition of the Receive FIFO threshold level at which an ISR[3] interrupt is generated. This
can be used to signal that the Receive FIFO is nearing overflow or that a predefined number of FIFO locations are
available for being read out in one block.
The actual FIFO trigger level is 8 x RxTrig[n], hence the selectable threshold granularity is eight.
Bits 3–0: TxTrig[n]
The TxTrig[n] bits allow definition of the Transmit FIFO threshold level at which the MAX14830 generates an ISR[4]
interrupt. This can be used to manage data flow to the Transmit FIFO. For example, if the trigger level is defined near
the bottom of the TxFIFO, the host knows that a predefined number of FIFO locations are available to be written to in
one block. Alternatively, if the trigger level is set near the top of the FIFO, the host is warned when the Transmit FIFO
is nearing overflow, if written to on a word-by-word basis.
The actual FIFO trigger level is 8 x TxTrig[n], hence the selectable threshold granularity is eight.
ADDRESS: 0x0F
MODE: R/W
BIT 7 6 5 4 3 2 1 0
NAME
Resume3 Resume2 Resume1 Resume0 Halt3 Halt2 Halt1 Halt0
RESET
0 0 0 0 0 0 0 0
ADDRESS: 0x10
MODE: R/W
BIT 7 6 5 4 3 2 1 0
NAME
RxTrig3 RxTrig2 RxTrig1 RxTrig0 TxTrig3 TxTrig2 TxTrig1 TxTrig0
RESET
1 1 1 1 1 1 1 1