Datasheet

4 Maxim Integrated
Quad Serial UART with 128-Word FIFOs
MAX14830
Figure 1. I
2
C Timing Diagram.................................................................... 13
Figure 2. SPI Timing Diagram
................................................................... 13
Figure 3. Transmit FIFO Signals
.................................................................. 18
Figure 4. Receive Data Format
................................................................... 19
Figure 5. Receive FIFO
........................................................................ 19
Figure 6. Midbit Sampling
...................................................................... 19
Figure 7. Clock Selection Diagram
................................................................ 20
Figure 8. 2x and 4x Baud Rates
.................................................................. 21
Figure 9. GPIO_ Clock Pulse Generator
............................................................ 22
Figure 10. Auto Transceiver Direction Control
....................................................... 23
Figure 11. Setup and Hold times in Auto Transceiver Direction Control
................................... 23
Figure 12. Single Transmitter Trigger Accuracy
...................................................... 24
Figure 13. Multiple Transmitter Synchronization Accuracy
.............................................. 25
Figure 14. Echo Suppression Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 15. Half-Duplex with Echo Suppression
...................................................... 26
Figure 16. Simplified Interrupt Structure
............................................................ 27
Figure 17. PLL Signal Path
...................................................................... 51
Figure 18. SPI Write Cycle
...................................................................... 58
Figure 19. SPI Read Cycle
...................................................................... 59
Figure 20. SPI Fast Read Cycle
.................................................................. 59
Figure 21. I
2
C START, STOP, and Repeated START Conditions ......................................... 60
Figure 22. Write Byte Sequence
.................................................................. 61
Figure 23. Burst Write Sequence
................................................................. 61
Figure 24. Read Byte Sequence
................................................................. 62
Figure 25. Burst Read Sequence
................................................................. 62
Figure 26. Acknowledge Bits
....................................................................63
Figure 27. Startup and Initialization Flow Chart
...................................................... 63
Figure 28. Logic-Level Translation
................................................................64
Figure 29. Interchip Synchronization
.............................................................. 64
LIST OF FIGURES