Datasheet

38 Maxim Integrated
Quad Serial UART with 128-Word FIFOs
MAX14830
STSInt—Status Interrupt Register
Bits 7, 6: No Function
Bit 5: ClockReady
The ClockReady bit is set high when the clock, the divider, and PLL have settled and the MAX14830 is ready for
data communication. The ClockReady bit only works with the crystal oscillator. It does not work with external clocking
through XIN.
The ClockReady status bit is cleared when the clock is disabled and is not cleared upon read. This bit can generate
an ISR[2]: STSInt interrupt, if enabled through STSIntEn[5].
Bit 4: No Function
Bits 3–0: GPI[n]Int
Each UART has four individually assigned GPIO outputs as follows: UART0: GPIO0–GPIO3, UART1: GPIO4–GPIO7,
UART2: GPIO8–GPIO11, UART3: GPIO12–GPIO15. For example, for UART0: Bit 0 is GPI0Int, Bit 1 is GPI1Int, Bit 2 is
GPI2Int, and Bit 3 is GPI3Int. See Table 1.
The GPI[n]Int interrupts are set high when a change of logic state occurs on the associated GPIO_ input, unless
disabled by the GPI[n]IntEn bits. GPI[n]Int is cleared upon reading. These interrupts can be selectively routed to the
ISR[2] interrupt bit through the STSIntEn[3:0].
Table 1. UART GPIO Assignments for GPIO Interrupts
ADDRESS: 0x08
MODE: R/COR
BIT 7 6 5 4 3 2 1 0
NAME
— —
ClockReady
—
GPI3Int GPI2Int GPI1Int GPI0Int
RESET
0 0 0 0 0 0 0 0
UART GPI3Int/GPI3IntEn GPI2Int/GPI2IntEn GPI1Int/GPI1IntEn GPI0Int/GPI0IntEn
UART0 GPIO3 GPIO2 GPIO1 GPIO0
UART1 GPIO7 GPIO6 GPIO5 GPIO4
UART2 GPIO11 GPIO10 GPIO9 GPIO8
UART3 GPIO15 GPIO14 GPIO13 GPIO12