Datasheet

33Maxim Integrated
Quad Serial UART with 128-Word FIFOs
MAX14830
LSRIntEn—Line Status Interrupt Enable Register
The LSR Interrupt Enable register allows routing of LSR interrupt bits to the ISR[0].
Bits 7, 6: No Function
Bit 5: NoiseIntEn
Set the NoiseIntEn bit high to enable routing the RxNoise interrupt to LSR[0]. If NoiseIntEn is set low, RxNoise is not
routed to LSR[0].
Bit 4: RBreakIEn
Set the RBreakIEn bit high to enable routing the RxBreak interrupt to LSR[0]. If RBreakIEn is set low, RxBreak is not
routed to LSR[0].
Bit 3: FrameErrIEn
Set the FrameErrIEn bit high to enable routing the FrameErr interrupt to LSR[0]. If FrameErrIEn is set low, FrameErr is
not routed to LSR[0].
Bit 2: ParityIEn
Set the ParityIEn bit high to enable routing the RxParityErr interrupt to LSR[0]. If ParityIEn is set low, RxParityErr is not
routed to the LSR[0].
Bit 1: ROverrIEn
Set the ROverrIEn bit high to enable routing the RxOverrun interrupt to LSR[0]. If ROverrIEn is set low, RxOverrun is
not routed to LSR[0].
Bit 0: RTimoutIEn
Set the RTimoutIEn bit high to enable routing the RTimeout interrupt to LSR[0]. If RTimoutIEn is set low, the RTimeout
is not routed to LSR[0].
ADDRESS: 0x03
MODE: R/W
BIT 7 6 5 4 3 2 1 0
NAME
— — NoiseIntEn RBreakIEn FrameErrIEn ParityIEn ROverrIEn RTimoutIEn
RESET
0 0 0 0 0 0 0 0