Datasheet

30 Maxim Integrated
Quad Serial UART with 128-Word FIFOs
MAX14830
Detailed Register Description
The MAX14830 has registers that are 8 bits wide.
RHR—Receive Hold Register
Bits 7 –0: RData[n]
The RHR is the bottom of the Receive FIFO and is the register used for reading data out of the Receive FIFO. It contains
the oldest (first received) character in the Receive FIFO. RHR[0] is the LSB of the character received at the RX_ input.
It is the first data bit of the serial-data word received by the receiver.
THR—Transmit Hold Register
Bits 7–0: TData[n]
The THR is the register that the host controller writes data to for subsequent UART transmission. This data is deposited
in the Transmit FIFO. THR[0] is the LSB. It is the first data bit of the serial-data word that the transmitter sends out, right
after the START bit.
ADDRESS: 0x00
MODE: R
BIT 7 6 5 4 3 2 1 0
NAME
RData7 RData6 RData5 RData4 RData3 RData2 RData1 RData0
RESET
X X X X X X X X
ADDRESS: 0x00
MODE: W
BIT 7 6 5 4 3 2 1 0
NAME
TData7 TData6 TData5 TData4 TData3 TData 2 TData1 TData0