Datasheet

3Maxim Integrated
Quad Serial UART with 128-Word FIFOs
MAX14830
AutoRTS Control..........................................................................26
AutoCTS Control
..........................................................................26
FIFO Interrupt Triggering
......................................................................26
Auto Software (XON/XOFF) Flow Control
.........................................................26
Transmitter Flow Control
....................................................................27
Receiver Overflow Control
..................................................................27
Power-Up and IRQ
..........................................................................27
Shutdown Mode
............................................................................27
Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Interrupt Enabling
.........................................................................28
Interrupt Clearing
.........................................................................28
Register Map
................................................................................ 28
Detailed Register Description
..................................................................30
Serial Controller Interface
....................................................................... 58
SPI Interface
...............................................................................58
MISO Operation
..........................................................................58
SPI Burst Access
.........................................................................58
Fast Read Cycle
..........................................................................59
I
2
C Interface ...............................................................................59
START, STOP, and Repeated START Conditions
.................................................59
Slave Address
...........................................................................60
Bit Transfer
..............................................................................61
Single-Byte Write
.........................................................................61
Burst Write
..............................................................................61
Single-Byte Read
.........................................................................62
Burst Read
..............................................................................62
Acknowledge Bits
........................................................................63
Applications Information
........................................................................ 63
Startup and Initialization
......................................................................63
Low-Power Operation
........................................................................63
Interrupts and Polling
........................................................................63
Logic-Level Translation
.......................................................................63
IO-Link Application
..........................................................................63
Typical Operating Circuit
....................................................................... 65
Chip Information
.............................................................................. 67
Package Information
........................................................................... 67
Revision History
.............................................................................. 68
TABLE OF CONTENTS (continued)