Datasheet

29Maxim Integrated
Quad Serial UART with 128-Word FIFOs
MAX14830
Register Map (continued)
*Denotes nonzero default reset value: ISR = 0x60, LCR = 0x05, FIFOTrgLvl = 0xFF, PLLConfig = 0x01, DIVLSB = 0x01,
CLKSource = 0x08, REVID = 0xB1.
†Denotes nonread/write value: RHR = R, THR = W, ISR = COR, SpclCharInt = COR, STSInt = R/COR,
LSR = R, TxFIFOLvl = R, RxFIFOLvl = R, REVID = R.
¥Each UART has four individually assigned GPIO outputs as follows: UART0: GPIO0–GPIO3, UART1: GPIO4–GPIO7, UART2:
GPIO8–GPIO11, UART3: GPIO12–GPIO15.
‡This register can only be programmed by accessing UART0.
#This register can only be directly addressed in I
2
C mode. Use extended addressing when operating in SPI mode.
REGISTER ADDR BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
GPIOs
GPIOConfg
¥
0x18 GP3OD GP2OD GP1OD GP0OD GP3Out GP2Out GP1Out GP0Out
GPIOData
¥
0x19 GPI3Dat GPI2Dat GPI1Dat GPI0Dat GPO3Dat GPO2Dat GPO1Dat GPO0Dat
CLOCK CONFIGURATION
PLLConfig*
‡
0x1A PLLFactor1 PLLFactor0 PreDiv5 PreDiv4 PreDiv3 PreDiv2 PreDiv1 PreDiv0
BRGConfig 0x1B — CLKDisabl 4xMode 2xMode FRACT3 FRACT2 FRACT1 FRACT0
DIVLSB 0x1C Div7 Div6 Div5 Div4 Div3 Div2 Div1 Div0
DIVMSB 0x1D Div15 Div14 Div13 Div12 Div11 Div10 Div9 Div8
CLKSource*
‡
0x1E CLKtoRTS — — — PLLBypass PLLEn CystalEn —
GLOBAL REGISTERS
GlobalRQ 0x1F 0 0 0 0
IRQ3 IRQ2 IRQ1 IRQ0
GloblComnd 0x1F GlbCom7 GlbCom6 GlbCom5 GlbCom4 GlbCom3 GlbCom2 GlbCom1 GlbCom0
SYNCHRONIZATION REGISTERS
TxSynch
#
0x20 CLKtoGPIO TxAutoDis TrigDelay SynchEn TrigSel3 TrigSel2 TrigSel1 TrigSel0
SynchDelay1
#
0x21 SDelay7 SDelay6 SDelay5 SDelay4 SDelay3 SDelay2 SDelay1 SDelay0
SynchDelay2
#
0x22 SDelay15
SDelay14 SDelay13 SDelay12 SDelay11 SDelay10 SDelay9 SDelay8
TIMER REGISTERS
TIMER1
#
0x23 Timer7 Timer6 Timer5 Timer4 Timer3 Timer2 Timer1 Timer0
TIMER2
#
0x24 TmrToGPIO Timer14 Timer13 Timer12 Timer11 Timer10 Timer9 Timer8
REVISION
REVID*
†#
0x25 1 0 1 1 0 0 1 1