Datasheet

28 Maxim Integrated
Quad Serial UART with 128-Word FIFOs
MAX14830
register to determine which UART is the source of the
interrupt. The interrupt sources are divided into top-level
and low-level interrupts. The top-level interrupts typically
occur more often and can be read out directly through
the ISR. The low-level interrupts typically occur less often
and their specific source can be read out through the
LSR, STSInt, or SpclChar registers. The three LSBs of the
ISR point to the low-level interrupt registers that contain
the detail of the interrupt source.
Interrupt Enabling
Every interrupt bit of the four interrupt registers can be
enabled or masked through an associated interrupt
enable register bit. These are the IRQEn, LSRIntEn,
SpclChrIntEn, and STSIntEn registers.
Interrupt Clearing
When an ISR interrupt is pending (i.e. any bit in ISR is
set) and the ISR is subsequently read, the ISR bits and
IRQ are cleared. Both the SpclCharInt and the STSInt
registers are also clear on read (COR). The LSR bits are
only cleared when the source of the interrupt is removed,
not when LSR is read.
Reading the GlobalIRQ register does not clear the IRQ
interrupt.
Register Map
(All default reset values are 0x00, unless otherwise noted. All registers are R/W, unless otherwise noted.)
REGISTER ADDR BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
FIFO DATA
RHR
†
0x00 RData7 RData6 RData5 RData4 RData3 RData2 RData1 RData0
THR
†
0x00 TData7 TData6 TData5 TData4 TData3 TData2 TData1 TData0
INTERRUPTS
IRQEn 0x01 CTSIEn RFifoEmtyIEn TFifoEmtyIEn TFifoTrgIEn RFifoTrgIEn STSIEn SpclChrIEn LSRErrIEn
ISR*
†
0x02 CTSInt RFifoEmptyInt TFifoEmptyInt TFifoTrigInt RFifoTrigInt STSInt SpCharInt LSRErrInt
LSRIntEn 0x03 — — RxNoiseIntEn RBreakIEn FrameErrIEn ParityIEn ROverrIEn RTimoutIEn
LSR*
†
0x04 CTSbit — RxNoise RxBreak FrameErr RxParityErr RxOverrun RTimeout
SpclChrIntEn 0x05 — — MltDrpIntEn BREAKIntEn XOFF2IntEn XOFF1IntEn XON2IntEn XON1IntEn
SpclCharInt
†
0x06 — — MultiDropInt BREAKInt XOFF2Int XOFF1Int XON2Int XON1Int
STSIntEn
¥
0x07 — — ClockRdyIntEn — GPI3IntEn GPI2IntEn GPI1IntEn GPI0IntEn
STSInt
†¥
0x08 — — ClockReady — GPI3Int GPI2Int GPI1Int GPI0Int
UART MODES
MODE1 0x09 IRQSel — — TrnscvCtrl RTSHiZ TXHiZ TxDisabl RxDisabl
MODE2 0x0A EchoSuprs MultiDrop
LoopBack SpecialChr RxEmtyInv RxTrgInv FIFORst RST
LCR* 0x0B
RTSbit
TxBreak ForceParity EvenParity ParityEn StopBits Length1 Length0
RxTimeOut 0x0C TimOut7 TimOut6 TimOut5 TimOut4 TimOut3 TimOut2 TimOut1 TimOut0
HDplxDelay 0x0D Setup3 Setup2 Setup1 Setup0 Hold3 Hold2 Hold1 Hold0
IrDA 0x0E — — TxInv RxInv MIR RTSInvert SIR IrDAEn
FIFOs CONTROL
FlowLvl 0x0F Resume3 Resume2 Resume1 Resume0 Halt3 Halt2 Halt1 Halt0
FIFOTrgLvl* 0x10 RxTrig3 RxTrig2 RxTrig1 RxTrig0 TxTrig3 TxTrig2 TxTrig1 TxTrig0
TxFIFOLvl
†
0x11 TxFL7 TxFL6 TxFL5 TxFL4 TxFL3 TxFL2 TxFL1 TxFL0
RxFIFOLvl
†
0x12 RxFL7 RxFL6 RxFL5 RxFL4 RxFL3 RxFL2 RxFL1 RxFL0
FLOW CONTROL
FlowCtrl 0x13 SwFlow3 SwFlow2 SwFlow1 SwFlow0 SwFlowEn GPIAddr AutoCTS AutoRTS
XON1 0x14 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
XON2 0x15 Bit7 Bi6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
XOFF1 0x16 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
XOFF2 0x17 Bit7
Bi6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0