Datasheet

19Maxim Integrated
Quad Serial UART with 128-Word FIFOs
MAX14830
The contents of the TxFIFO and RxFIFOs are both
cleared through MODE2[1]: FIFORst.
To halt transmission, set MODE1[1]: TxDisabl to 1. After
MODE1[1] is set, the transmitter completes transmission
of the current character and then ceases transmission.
The TX_ output logic can be inverted through IrDA[5]:
TxInv. If not stated otherwise, all transmitter logic
described in this data sheet assumes that IrDA[5] is 0.
Receiver Operation
The receiver expects the format of the data at RX_ to be
as shown in Figure 4. The quiescent logic state is high
and the first bit (the START bit) is logic-low. The receiver
samples the data near the midbit instant (Figure 4). The
received words and their associated errors are depos-
ited into the Receive FIFO. Errors and status informa-
tion are stored for every received word (Figure 5). The
host reads the data out of the Receive FIFO through
the Receive Hold Register (RHR), oldest data first. The
status information of the most recently read word in the
RHR is located in the Line Status Register (LSR). After a
word is read out of the RHR, the LSR contains the status
information for that word.
The following three error conditions are determined for
each received word: parity error, framing error, and
noise on the line. Line noise is detected by checking the
consistency of the logic of the three samples (Figure 6).
Figure 5. Receive FIFO
Figure 4. Receive Data Format
Figure 6. Midbit Sampling
RECEIVED DATA
LSB
START D0 D1 D2 D3 D4 D5 D6 D7 PARITY STOP STOP
MSB
MID BIT
SAMPLING
RECEIVE FIFO
FIFOTrgLvl[7:4]
TRIGGER
ISR[3]
WORD ERROR 128
RxFIFOLvl
4
3
2
1
TIMEOUT
EMPTY
ERRORS
OVERRUN
LSR[1]
RECEIVED
DATA
RHR
RECEIVER RX_
I
2
C/SPI INTERFACE
LSR[0]
ISR[6]
LSR[5:2]
CURRENT FILL LEVEL
1
RX_
BAUD
BLOCK
23456789
ONE BIT PERIOD
10 11
MAJORITY
CENTER
SAMPLER
12 13 14 15 16
A