Datasheet

MAX14821
IO-Link Device Transceiver
26Maxim Integrated
SPI Interface
The device communicates through an SPI-compatible
4-wire serial interface. The interface has three inputs—
clock (SCLK), chip select (CS), and data in (SDI)—and
one output, data out (SDO). The maximum SPI clock rate
for the device is 12MHz. The SPI interface complies with
clock polarity CPOL = 0 and clock phase CPHA = 0 (see
Figure 11 and Figure 12).
The SPI interface is not available when V
5
or V
L
are not
present.
Figure 11. SPI Write Cycle
Figure 12. SPI Read Cycle
R0 D7 D6 D5 D4 D3 D2 D1 D0
SCLK
R_ = REGISTER ADDRESS
D_ = DATA BIT
= CLOCK EDGE THAT INITIATES LATCHING OF SDI DATA
SDI
W 00000
R1
CS
SDI
SDO
SCLK
RR1R000X X000
CS
D7 D6 D5 D4 D3 D2 D1 D0
R_ = REGISTER ADDRESS
D_ = DATA BIT
= CLOCK EDGE THAT INITIATES LATCHING OF SDI DATA
= CLOCK EDGE THAT INITIATES WRITING OF SDO DATA