Datasheet

MAX14820
IO-Link Device Transceiver
26Maxim Integrated
SPI Interface
The device communicates through an SPI-compatible
4-wire serial interface. The interface has three inputs—
clock (SCLK), chip select (CS), and data in (SDI)—and
one output, data out (SDO). The maximum SPI clock rate
for the device is 12MHz. The SPI interface complies with
clock polarity CPOL = 0 and clock phase CPHA = 0 (see
Figure 10 and Figure 11).
The SPI interface is not available when V
5
or V
L
are not
present.
Figure 10. SPI Write Cycle
Figure 11. SPI Read Cycle
R0 D7 D6 D5 D4 D3 D2 D1 D0
SCLK
R_ = REGISTER ADDRESS
D_ = DATA BIT
= CLOCK EDGE THAT INITIATES LATCHING OF SDI DATA
SDI
W 00000
R1
CS
CS
SCLK
SDI
00 000R1R0R
D7 D6 D5 D4 D3 D2 D1 D0
SDO
XX
R_ = REGISTER ADDRESS
D_ = DATA BIT
= CLOCK EDGE THAT INITIATES LATCHING OF SDI DATA
= CLOCK EDGE THAT INITIATES WRITING OF SDO DATA