Datasheet

MAX14820
IO-Link Device Transceiver
14Maxim Integrated
Pin Configuration
Pin Description
PIN NAME FUNCTION
1 LDOIN
5V Linear Regulator Input. Bypass LDOIN to GND with a 0.1FF ceramic capacitor.
2 V
5
5V Power-Supply Input and 5V Linear Regulator Output. Bypass V
5
to GND with a 0.1FF ceramic capacitor
for 10mA load capability. Add the recommended compensation network to increase the source capability to
30mA. See the 5V and 3.3V Linear Regulators section for more information.
3 LDO33
3.3V Linear Regulator Output. Bypass LDO33 to GND with a 1FF ceramic capacitor.
4
IRQ Active-Low Interrupt Request Output. IRQ is a push-pull output referenced to V
L
.
5 SCLK SPI Clock Input
6
CS
Active-Low SPI Chip-Select Input
7 SDO SPI Serial-Data Output
8 SDI SPI Serial-Data Input
9 V
L
Logic-Level Supply Input. V
L
defines the logic levels on all the logic inputs and outputs. Bypass V
L
to GND
with a 0.1FF ceramic capacitor.
10 I.C. Internally Connected. Connect to V
L
or leave unconnected. It is recommended to connect to V
L
.
11 TXQ
Transmit Level Input. The logic on the C/Q output is the inverse logic level of the signals on the TXC and
TXQ inputs. TXQ is ANDed with TXC. Drive TXQ high if not in use.
12 TXC
Transmit Communication Input. The logic on the C/Q output is the inverse logic level of the signals on the
TXC and TXQ inputs. TXC is ANDed with TXQ. Drive TXC high if not in use.
13 TXEN Transmitter Enable. Drive TXEN high to enable the C/Q transmitter. TXEN is referenced to V
L
.
23
24
22
21
8
7
9
V
5
IRQ
SCLK
CS
10
LDOIN
LI WU RX UV TXEN
12
DO
456
1718 16 14 13
V
CC
V
P
I.C.
V
L
SDI
SDO
*EP
*CONNECT EXPOSED PAD TO GND.
LDO33
LO
3
15
C/Q
20
11
TXQ
GND
19
12
TXC
DI
TQFN
(4mm × 4mm)
TOP VIEW
+
MAX14820