Datasheet

PD0 CLOCK IN
t
SSTRB
t
CSH
t
CONV
t
SCK
SSTRB
SCLK
DOUT
t
CSS
t
DO
NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
CS
Figure 10. Internal Clock Mode SSTRB Detailed Timing
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
14 ______________________________________________________________________________________
processor’s convenience, at any clock rate from 0MHz
to 2MHz. SSTRB goes low at the start of the conversion
and then goes high when the conversion is complete.
SSTRB is low for a maximum of 7.5µs (SHDN = FLOAT),
during which time SCLK should remain low for best
noise performance.
An internal register stores data when the conversion is
in progress. SCLK clocks the data out of this register at
any time after the conversion is complete. After SSTRB
goes high, the next falling clock edge produces the
MSB of the conversion at DOUT, followed by the
remaining bits in MSB-first format (Figure 9). CS does
not need to be held low once a conversion is started.
Pulling CS high prevents data from being clocked into
the MAX146/MAX147 and three-states DOUT, but it
does not adversely affect an internal clock mode
conversion already in progress. When internal clock
mode is selected, SSTRB does not go into a high-
impedance state when CS goes high.
Figure 10 shows the SSTRB timing in internal clock
mode. In this mode, data can be shifted in and out of
the MAX146/MAX147 at clock rates exceeding 2.0MHz
if the minimum acquisition time (t
ACQ
) is kept above
1.5µs.
SSTRB
CS
SCLK
DIN
DOUT
14 8
12
18
20
24
START
SEL2 SEL1 SEL0
UNI/
BIP
SGL/
DIF
PD1 PD0
B11
MSB
B10 B9 B2 B1
B0
LSB
FILLED WITH
ZEROS
IDLE
CONVERSION
7.5µs MAX
(SHDN = FLOAT)
2 3 5 6 7 9 10 11 19 21 22 23
t
CONV
ACQUISITION
(f
SCLK
= 2MHz)
IDLE
A/D STATE
1.5µs
Figure 9. Internal Clock Mode Timing