Datasheet

During undervoltage and overvoltage events, the internal
diodes pull V
DD
/V
SS
supplies up/down. An advantage
of this scheme is that the input impedance is high and
currents do not flow though the MAX14756/MAX14757/
MAX14758 during overvoltage and undervoltage events.
The input voltages must be limited to the voltages speci-
fied in the Absolute Maximum Ratings section.
Figure 9. Input Overvoltage and Undervoltage Clamping
Figure 10. Beyond-the-Rail Application
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
16 TSSOP U16+1 21-0066 90-0117
V
DD
V
SS
R
LIM
V
IN
A1
B1
R
LIM
V
IN
A2
B2
R
LIM
V
IN
A3
B3
R
LIM
V
IN
A4
B4
MAX14756
MAX14757
MAX14758
V+
R
V
IN
V
DD
V
SS
V-
B_
A_
MAX14756/MAX14757/
MAX14758
Quad SPST +70V Analog Switches
www.maximintegrated.com
Maxim Integrated │ 11
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.