Datasheet

When the crystal is loaded as specified, i.e., C
load
=
C
spec
, the frequency pulling equals zero.
Data Filter
The data filter is implemented as a 2nd-order lowpass
Sallen-Key filter. The pole locations are set by the
combination of two on-chip resistors and two external
capacitors. Adjusting the value of the external capacitors
changes the corner frequency to optimize for different
data rates. The corner frequency should be set to approxi-
mately 1.5 times the fastest expected data rate from the
transmitter. Keeping the corner frequency near the data
rate rejects any noise at higher frequencies, resulting in
an increase in receiver sensitivity.
The configuration shown in Figure 1 can create a
Butterworth or Bessel response. The Butterworth filter
offers a very flat amplitude response in the passband and
a roll-off rate of 40dB/decade for the two-pole filter. The
Bessel filter has a linear phase response, which works
well for filtering digital data. To calculate the value of C5
and C6, use the following equations along with the coef-
ficients in Table 1:
( )( )
( )
( )( )
( )
c
c
b
C5
a 100k f
a
C6
4 100k f
=
Ωπ
=
Ωπ
where f
C
is the desired 3dB corner frequency.
For example, to choose a Butterworth filter response with
a corner frequency of 5kHz:
( )( )( )( )
( )( )( )( )
1.000
C5 450pF
1.414 100k 3.14 5kHz
1.414
C6 225pF
4 100k 3.14 5kHz
= ≈
Ω
= ≈
Ω
Choosing standard capacitor values changes C5 to 470pF
and C6 to 220pF, as shown in the Typical Application
Circuit.
Data Slicer
The purpose of the data slicer is to take the analog output
of the data filter and convert it to a digital signal. This is
achieved by using a comparator and comparing the analog
input to a threshold voltage. The threshold voltage is set
by the voltage on DSN, which is connected to the negative
input of the data slicer comparator. The positive input is
connected to the output of the data filter internally, and also
the DSP pin for use with some data slicer configurations.
The suggested data slicer configuration uses a resistor
(R1) connected between DSN and DSP with a capacitor
(C4) from DSN to DGND (Figure 2). This configuration
averages the analog output of the filter and sets the
threshold to approximately 50% of that amplitude. With
this configuration, the threshold automatically adjusts as
the analog signal varies, minimizing the possibility for
errors in the digital data. The sizes of R1 and C4 affect
how fast the threshold tracks the analog amplitude. Be
sure to keep the corner frequency of the RC circuit lower
than the lowest expected data rate.
Note that a long string of zeros or ones can cause the
threshold to drift. This configuration works best if a coding
scheme, such as Manchester code, which has an equal
number of zeros and ones, is used.
Peak Detector
The peak detector output (PDOUT), in conjunction with
an external RC filter, creates a DC output voltage equal
to the peak value of the data signal. The resistor provides
a path for the capacitor to discharge, allowing the peak
Figure 1. Sallen-Key Lowpass Data Filter
Table 1. Coefficents to Calculate C5 and C6
FILTER TYPE a b
Butterworth
(Q = 0.707)
1.414 1.000
Bessel
(Q = 0.577)
1.3617 0.618
19
DSP
C6
C5
R
DF2
100kΩ
R
DF1
100kΩ
RSSI
21
OPP
22
DF
MAX1470
MAX1470 315MHz Low-Power, +3V Superheterodyne
Receiver
www.maximintegrated.com
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