Datasheet

(V
DDF
= V
DD
= 4.5V to 5.5V, V
SSF
= V
SS
= 0V, f
CLK
= 4.0MHz, T
A
= T
MIN
to T
MAX
. Typical values are at V
DDF
= V
DD
= 5.0V, V
SSF
= V
SS
= 0V, T
A
= +25°C, unless otherwise noted.) (Note 1)
MAX1464 Low-Power, Low-Noise Multichannel
Sensor Signal Processor
www.maximintegrated.com
Maxim Integrated │ 5
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
LARGE OP AMP
Input Offset Voltage V
OS
_
LG
0 ±6 mV
Input Bias Current I
B
_
LG
±225 nA
DC Gain A
VOL
_
LG
OUTnLG = 0.5V to 4.5V (n = 1 or 2),
R
LOAD
= ∞
100 dB
Gain Bandwidth Product GBW_
LG
A
VOL_LG
= +1V/V 4.0 MHz
Slew Rate SR_
LG
A
VOL_LG
= +1V/V 3.2 V/µs
Common-Mode Input Range CMR_
LG
V
SS
+
0.02
V
DD
-
0.02
V
Common-Mode Rejection Ratio CMRR_
LG
V
CM OPAMP
= V
SS
to V
DD
70 dB
Power-Supply Rejection Ratio PSRR_
LG
At DC 70 dB
Input-Referred Noise Voltage V
N
_
LG
0.1Hz to 1kHz 19
µV
RMS
0.1Hz to 1MHz 160
Output-Voltage High V
OH
_
LG
R
LOAD
= ∞ V
DD
- 0.1
V
R
LOAD
= 1kW to V
SS
V
DD
- 0.125
Output-Voltage Low V
OL
_
LG
R
LOAD
= ∞ 0.03
V
R
LOAD
= 1kΩ to V
DD
0.13
Output Source Current I
SRC
_
LG
V
OUTnLG
= V
OH_LG
, R
LOAD
= 1kΩ to V
SS
-4.9 mA
Output Sink Current I
SNK
_
LG
V
OUTnLG
= V
OL_LG
, R
LOAD
= 1kΩ to V
DD
4.9 mA
Maximum Output Load
Capacitance
C
L
_
LG
R
LOAD
= ∞, phase margin > 55° 200 pF
OP-AMP SWITCH
Analog Signal Range V
SW
V
SS
V
DD
V
On-Resistance R
ON
5 kΩ
Off-Isolation V
ISO
80 dB
DIGITAL-TO-ANALOG CONVERTER
Resolution RES
DAC
16 Bits
Integral Nonlinearity INL
DAC
3 Bits
Differential Nonlinearity DNL
DAC
±1 Bits
Offset Error V
DAC OS
DAC ref = V
DD
, DAC data = 0000h
V
DD
/2
- 0.06
V
DD
/2
+ 0.06
V
Bit Weight BW
DAC
DAC ref = 5VDC 91.55 µV/LSB
Power-Supply Rejection PSR
DAC
At DC, DAC ref = V
REF
0.02 %FS
Output Noise ON
DAC
DAC buffer is the small op amp ±3 LSB
Output Settling Time ST
DAC
To 0.1% of nal value 250 µs
PULSE-WIDTH MODULATOR
Resolution RES
PWM
(Note 6) 12 Bits
Period P
PWM
f
CLK
= 4.0MHz 8.192 ms
Electrical Characteristics (continued)