Datasheet

Table 40. Interface Mode Register (IMR)
Decoding
Table 41. Instruction Set
MAX1464 Low-Power, Low-Noise Multichannel
Sensor Signal Processor
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IRSD DESCRIPTION
0000
Place the MAX1464 into a 4-wire serial interface
(DI cannot be connected to DO).
0001
Place the MAX1464 into a 3-wire serial interface
(DI can be externally connected to DO).
0010–1111 Unused.
OP CODE (hex) MNEMONIC OPERATION
TWO’S
COMP
NO. OF
REGISTERS
INVOLVED
NO. OF
CYCLES
NO. OF
BYTES
0X LDX Load register X from program memory. Y 1 3 3
1X CLX Clear X-reg. Y 1 1 1
2X ANX A-reg = A-reg AND X-reg. N 2 1 1
3X ORX A-reg = A-reg OR X-reg. N 2 1 1
4X ADX A-reg = A-reg ADD X-reg. Y 2 1 1
5X STX X-reg = A-reg. Y 2 1 1
6X SLX Shift left X-reg. N 1 or 2 1 1
7X SRX Shift right X-reg propagating sign bit. Y 1 1 1
8X INX X-reg = X-reg + 1. Y 1 1 1
9X DEX X-reg = X-reg - 1. Y 1 1 1
AX NGX X-reg = NOT X-reg. N 1 1 1
BX BPX Branch positive I-reg by amount in X-reg. Y 2 1 1
CX BNX Branch not zero I-reg by amount in X-reg. Y 2 1 1
DX RDX A-reg = CPU port-X. Y 1 1 1
EX WRX CPU port-X = A-reg. Y 1 1 1
F3 MLT
A-reg | M-reg = M-reg multiplied by
N-reg; register op code must be 3h.
Y 3 16 1