Datasheet

Description:
Perform a 16-bit logical AND operation, bit for bit, on
the contents of the A-register and the contents of the
Xregister. Store the 16-bit result back into the A-register.
The previous contents of the A-register are overwritten
and lost.
Register X can be any of the 16 CPU registers.
PC is incremented once to point to the next instruction in
program memory.
Two’s-complement data format is not preserved.
No branching occurs.
No other registers are affected.
ORX OR Register X with Register A
Op-code: 0011 XXXXBINARY 3Xh
Operation:
A-register ← A-register OR X-register
PC-register ← PC + 1 (point to next instruction)
CPU Cycles required:
1 cycle
Description:
Perform a 16-bit logical OR operation, bit for bit, on
the contents of the A-register and the contents of the
X-register. Store the 16-bit result back into the A-register.
The previous contents of the A-register are overwritten
and lost.
Register X can be any of the 16 CPU registers.
PC is incremented once to point to the next instruction in
program memory.
Two’s-complement data format is not preserved.
No branching occurs.
No other registers are affected.
ADX ADD Register X to Register A
Op-code: 0100 XXXXBINARY 4Xh
Operation:
A-register ← A-register + X-register
PC-register ← PC + 1 (point to next instruction)
CPU Cycles required:
1 cycle
Description:
Perform a 16-bit arithmetic addition of the A-register and
the contents of the X-register. Store the low 16 bits of the
result back into the A-register. Any overflow bit resulting
from the addition operation is lost. The previous contents
of the A-register are overwritten and lost.
Register X can be any of the 16 CPU registers.
PC is incremented once to point to the next instruction in
program memory.
Two’s-complement data format is preserved.
No branching occurs.
No other registers are affected.
STX Store Register X
Op-code: 0101 XXXXBINARY 5Xh
Operation:
X-register ← A-register
PC-register ← PC + 1 (point to next instruction)
CPU Cycles required:
1 cycle
Description:
Perform a 16-bit move operation from the A-register into
the X-register. The A-register contents are unchanged.
The previous contents of the X-register are overwritten
and lost.
Register X can be any of the 16 CPU registers.
PC is incremented once to point to the next instruction in
program memory.
Two’s-complement data format is preserved.
No branching occurs.
No other registers are affected.
SLX Shift Left Register X
Op-code: 0110 XXXXBINARY 6Xh
1415 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
BIT:
14
15 13 12 11 10 9 8 7 6 5 4 3 2 1 0BIT:
1415 13 12 11 10 9 8 7 6 5 4 3 2 1 0BIT:
REGISTER X
Operation when X 6h:
REGISTER R6
REGISTER M: R4
Operation when X = 6h:
PC-register ← PC + 1 (point to next instruction)
CPU Cycles required:
1 cycle
MAX1464 Low-Power, Low-Noise Multichannel
Sensor Signal Processor
www.maximintegrated.com
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