Datasheet

MAX1454
Precision Sensor Signal Conditioner
with Overvoltage Protection
17Maxim Integrated
Table 11. DIGMODETIME Setting*
(DIGMODETIME[3:0] )
Table 12. CTRLREP Setting
(CTRLREP[2:0])
Table 13. Temperature Index Typical Values
*Parts ship with a CTRLREP setting of 111.
*Wait times specified are based on a typical oscillator fre-
quency of 1MHz. Wait times are proportional to the oscillation
frequency. Actual wait times depend on the factory-trimmed
oscillator frequency.
**Parts ship with a DIGMODETIME setting of 1111.
Table 14. IRSA Decoding (IRSA[3:0])
DIGMODETIME[3:0] DESCRIPTION
0000
Part stays in digital mode for 1ms
after power-up (for each repetition of
the control word)
0001 2ms wait
0010 3ms wait
0011 4ms wait
0100 5ms wait
0101 8ms wait
0110 10ms wait
0111 15ms wait
1000 20ms wait
1001 25ms wait
1010 to 1111 30ms wait**
CTRLREP[2:0] DESCRIPTION
000 1 control word expected
001 1 control word expected
010 2 control words expected
011 3 control words expected
100 4 control words expected
101 5 control words expected
110 6 control words expected
111 Part powers up in digital mode*
TEMPERATURE TEMPINDEX[7:0]
(NC)
DECIMAL HEXADECIMAL
-40 27 1B
+25 70 46
+85 109 6D
[phone]
IRSA[3:0] DESCRIPTION
0000 Write IRSD[3:0] to DHR[3:0] (data hold register).
0001 Write IRSD[3:0] to DHR[7:4] (data hold register).
0010 Write IRSD[3:0] to DHR[11:8] (data hold register).
0011 Write IRSD[3:0] to DHR[15:12] (data hold register).
0100 Reserved.
0101 Reserved.
0110
Write IRSD[3:0] to ICRA[3:0] or IEEA[3:0] (internal calibration register address or internal flash memory
address nibble 0).
0111 Write IRSD[3:0] to IEEA[7:4] (internal flash memory address nibble 1).
1000 Write IRSD[3:0] to IRSP[3:0] or IEEA[10:8] (interface register set pointer where IRSP[2:0] is IEEA[10:8]).
1001 Write IRSD[3:0] to CRIL[3:0] (command register to internal logic).
1010 Write IRSD[3:0] to ATIM[3:0] (analog timeout value on read).
1011 Write IRSD[3:0] to ALOC[3:0] (analog location).
1100 Write IRSD[0] to ALOC[4] (analog location).
1101
Write IRSD[0] to the burst mode enable bit (BURSTEN). See the Burst Mode Operation section for details
regarding read/write operations in this mode. Logic 1 enables burst mode.
1100 to 1111 Reserved.