Datasheet

MAX1454
Precision Sensor Signal Conditioner
with Overvoltage Protection
15Maxim Integrated
Table 4. Configuration Register 2 (CONFIG2[15:0])
Table 5. Power-Up Configuration Register (PWRUPCFG[15:0])
Table 6. PGA Setting (PGA[4:0])
BIT NAME DESCRIPTION
15:7 Reserved Reserved. Set to logic 0.
6 ENFDET Enable fault-detection circuitry. Logic 1 enables fault detection.
5:4 REFRATE[1:0] DAC register refresh rate during fixed analog mode
3 ENPULLUP Enable internal pullup resistor on OUT/DIO pin. Logic 1 enables pullup.
2:1 READDLY[1:0] Number of byte times the part waits before responding to read requests
0 EXCIMODE Logic 1 for voltage excitation mode, logic 0 for current excitation mode
BIT NAME DESCRIPTION
15:7 Reserved Reserved. Set to logic 0.
6:3 DIGMODETIME[3:0] Number of ms the part waits to receive a control word before switching to analog mode
2:0 CTRLREP[2:0] Number of repetitions of the control word required to switch the part into digital mode
PGA[4:0] PGA GAIN (V/V) PGA[4:0] PGA GAIN (V/V)
00000 6 10000 144
00001 7 10001 176
00010 9 10010 208
00011 11 10011 256
00100 12 10100 288
00101 14 10101 352
00110 18 10110 416
00111 22 10111 512
01000 28 11000 576
01001 36 11001 704
01010 44 11010 832
01011 52 11011 1024
01100 64 11100 1152
01101 80 11101 1408
01110 96 11110 1664
01111 112 11111 2048