Datasheet

MAX1454
Precision Sensor Signal Conditioner
with Overvoltage Protection
14Maxim Integrated
To write to a flash memory location in burst mode, the
user simply writes DHR[3:0], followed by DHR[7:4].
Since the internal counter keeps track of the memory
address, there is no need to send address information
to the part. After DHR[7:4] is written, a write command
to the flash memory is automatically generated, the data
in DHR[7:0] is written to the memory, and the address
counter is incremented. If the user wishes to skip certain
memory locations, first exit burst mode (by writing a 0 to
BURSTEN), then program a new starting address. The
user can now reenable burst mode again.
During burst read operations, the device waits for a
read command before sending out data whose address
is derived from the internal counter. To start burst read
mode, first program the flash memory address into
IEEA[10:0]. Next, write a 1 to BURSTEN to enable burst
mode. The IRSP register must then be programmed
to 0 (through an IRSA = 8 command). Then, send the
flash memory read (RdEEP) CRIL command to initiate
an internal read; the device sends the contents of the
flash memory out of the DIO/OUT pin through the serial
interface. Similar to the burst write operation, the burst
read operation does not skip memory locations. To skip
memory locations, first write a zero to BURSTEN to end
burst mode. Next, change the memory address bits
using the corresponding command bytes. Once the
desired starting address is loaded, reenable burst mode
to resume burst reading.
Always disable burst mode (IRSD = 0000 when IRSA =
1101) after burst reading/writing all the locations. This is
necessary to continue in digital programming mode after
all the burst read/writes are complete.
Note: Use burst mode to program a maximum of 1024
locations. Care must be taken to avoid additional writes
to prevent unintentionally rewriting locations. The internal
address counter wraps around to address 0x000 after
reaching address 0x3FF.
Table 2. Registers
Register Map
Table 3. Configuration Register 1 (CONFIG1[15:0])
REGISTER DESCRIPTION
CONFIG1 Configuration Register 1
CONFIG2 Configuration Register 2
ODAC Offset DAC
OTCDAC Offset Temperature Coefficient DAC
FSODAC Full-Span Output DAC
FSOTCDAC Full-Span Output Temperature Coefficient DAC
PWRUPCFG Power-Up Configuration
BIT NAME DESCRIPTION
15:11 PGA[4:0] Programmable-gain amplifier setting
10 PGA Sign Logic 1 inverts IN- and IN+ polarity
9 IRO Sign Logic 1 for positive input-referred offset (IRO), logic 0 for negative input-referred offset (IRO)
8:5 IRO[3:0] Input-referred coarse-offset adjustment
4:3 CMRATIO[1:0] Bridge driver current-mirror ratio
2 Reserved Set to logic 0
1 ODAC Sign Logic 1 for positive offset DAC output, logic 0 for negative offset DAC output
0 OTCDAC Sign Logic 1 for positive offset TC DAC output, logic 0 for negative offset TC DAC output